A lateral double-diffused metal-oxide-semiconductor field effect transistor includes a silicon semiconductor structure, first and second gate structures, and a trench dielectric layer. The first and second gate structures are disposed on the silicon semiconductor structure and separated from each other in a lateral direction. The trench dielectric layer is disposed in a trench in the silicon semiconductor structure and extends at least partially under each of the first and second gate structures in a thickness direction orthogonal to the lateral direction.

A method of making a monolithic three dimensional NAND string is provided. A stack of alternating layers of a first material and a second material different from the first material is formed over a substrate. The stack is etched to form at least one opening in the stack. A charge storage material layer is formed on a sidewall of the at least one opening. A tunnel dielectric layer is formed on the charge storage material layer in the at least one opening. A semiconductor channel material is formed on the tunnel dielectric layer in the at least one opening. The first material layers are selectively removed to expose side wall of the charge storage material layer. A blocking dielectric is formed on the exposed side wall of the charge storage material layer. Control gates are formed on the blocking dielectric.

Systems, methods, and apparatus for an improved body tie construction that produces all the benefits of conventional body tie (H-gate, T-gate), without the limitations and degradations associated with those constructions are described. The improved body tie construction is configured to have a lower resistance body tie when the transistor is off (Vg approximately 0 volts). When the transistor is on (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie.

A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array of fins disposed thereon. Spacers are then formed on sidewalls of fins of the array. Pillars are formed between and adjacent the spacers. A gate having dummy gate material is formed over the structure, the gate extending laterally across the spacers and fins of the array. The dummy gate material and spacers are removed from the gate to form work-function (WF) metal trenches defined by the pillars and fins within the gate. The WF metal trenches have a first trench width. A thickness of the pillars is adjusted to provide a second trench width, different from the first trench width, for the WF metal trenches. A WF metal structure is disposed within the WF metal trenches.

A 3D memory has multiple memory layers stacked on top of a substrate. Word lines in different memory layers are connected respectively to different columns of contact pads in the substrate directly under the multiple memory layers. The connection is accomplished by creating vertical shifts above each contact pad and creating a vertical word line VIA connecting to the contact pad. For a given memory layer and its column of vertical word line VIAs, an auxiliary vertical shaft down to the memory layer is formed between each vertical word line VIA and an adjacent word line. The auxiliary vertical shaft is contiguous with the vertical shift allowing access to the vertical word line VIA. The auxiliary vertical shaft also enables excavating a lateral space between the word line and the vertical word line VIA. Filling the space with a conductive material completes a conductive path from the word line to the contact pad.

A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.

A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

There is provided a semiconductor device including: a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode layer that is provided on the gate insulating film and contains impurity ions; and source or drain regions that are provided on the semiconductor substrate on both sides of the gate electrode layer and contain conductive impurities, in which a concentration of the impurity ions in the gate electrode layer is higher than concentrations of the conductive impurities in the source or drain regions.

Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first sacrificial layer. A first hardmask layer is formed on the second sacrificial layer, and a second hardmask layer is formed on the first hardmask layer and patterned. The first hardmask layer is laterally recessed in a lateral direction under the second hardmask layer. The first and second sacrificial layers are etched to a corresponding width of the first hardmask layer. A spacer layer is formed on the fin, the first sacrificial layer, second sacrificial layer, the first hardmask layer and the second hardmask layer. The spacer layer is etched until it remains on a sidewall of the first sacrificial layer, the second sacrificial layer and the first hardmask layer, wherein the first and second sacrificial layers form the dummy gate.

An image sensor may include a plurality of pixels that each contain a photodiode. The pixels may include deep photodiodes for near infrared applications. The photodiodes may be formed by growing doped epitaxial silicon in trenches formed in a substrate. The doped epitaxial silicon may be doped with phosphorus or arsenic. The pixel may include additional n-wells formed by implanting ions in the substrate. Isolation regions formed by implanting boron ions may isolate the n-wells and doped epitaxial silicon. The doped epitaxial silicon may be formed at temperatures between 500 C. and 550 C. After forming the doped epitaxial silicon, laser annealing may be used to activate the ions. Chemical mechanical planarization may also be performed to ensure that the doped epitaxial silicon has a flat and planar surface for subsequent processing.