A cell structure of a silicon carbide MOSFET device, comprising a first conductivity type drift region (3) located above a first conductivity type substrate (2). A main trench is provided in the surface of the first conductivity type drift region (3); a Schottky metal (4) is provided on the bottom and sidewalls of the main trench; a second conductivity type well region (7) is provided in the surface of the first conductivity type drift region (3) and around the main trench; a source region (8) is provided in the surface of the well region (7); a source metal (10) is provided above the source region (8); a gate insulating layer (6) and a gate (5) split into two parts are provided above the sides of the source region (8), the well region (7), and the first conductivity type drift region (3) close to the main trench.

The present application discloses an SiC MOSFET device, including an SiC epitaxial layer in which a trench gate is formed, wherein a first bottom doped region is formed below a bottom surface of a gate trench, a second deep doped region with spacing from the gate trench is formed in the SiC epitaxial layer, the first bottom doped region is connected to a source so that voltage borne by a gate dielectric layer on the bottom surface of the gate trench is determined by gate-source voltage; the second deep doped region extends downward from a top surface of the SiC epitaxial layer, and a bottom surface of the second deep doped region is located below a bottom surface of the first bottom doped region; a top of the second deep doped region is connected to the source. The present application further discloses a method for manufacturing an SiC MOSFET device.

A silicon carbide semiconductor device includes, on a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a first semiconductor region of the first conductivity type selectively provided on a first side of the third semiconductor layer opposite to a second side thereof facing the silicon carbide semiconductor substrate, second semiconductor regions of the second conductivity type that have an impurity concentration higher than that of the second semiconductor layer, trenches, gate electrodes provided via gate insulating films, an interlayer insulating film, a first electrode, and a second electrode. The first semiconductor region is thinner than a portion of the third semiconductor layer between the first semiconductor region and the second semiconductor layer.

A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a source in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure comprising a body ring structure in the epitaxial layer, forming a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure.

Various embodiments of the present disclosure are directed towards an integrated chip comprising a gate electrode disposed on a substrate between a pair of source/drain regions. A dielectric layer is over the substrate. A field plate is disposed on the dielectric layer and laterally between the gate electrode and a first source/drain region in the pair of source/drain regions. The field plate comprises a first field plate layer and a second field plate layer. The second field plate layer extends along sidewalls and a bottom surface of the first field plate layer. The first and second field plate layers comprise a conductive material.

A bipolar transistor includes a sub-collector doped with a first dopant type and situated in a semiconductor substrate, a device layer doped with the first dopant type situated over the sub-collector, and a shallow trench isolation (STI) situated in the device layer and bordering a collector of the bipolar transistor. The bipolar transistor further includes a Reduced Surface Layer (RESURF) region doped with a second dopant type opposite the first dopant type situated between the collector and the STI, wherein the RESURF region protects against breakdown of the bipolar transistor.

A semiconductor device includes a first electrode, a first semiconductor region of a first type including first and second regions, second semiconductor regions of a second type on the first region, third semiconductor regions of the first type on the second semiconductor regions, a second electrode electrically connected to the third semiconductor regions, first structures in the first region, each of which includes an insulating region and a conductive region, second structures in the second region, each of which includes an insulating region and a conductive region, a third electrode surrounding the first and second structures, a first insulating portion between the second semiconductor region and the third electrode, a second insulating portion above the second region, and a wiring portion above the second insulating portion and electrically connected to the third electrode.

A method for manufacturing an injection-enhanced insulated-gate bipolar transistor, comprising the following steps: an n-type substrate (12) is provided; a p-type doped layer (14) is formed on the n-type substrate (12); a hard layer (20) is formed on the p-type doped layer (14); a groove (40) extending to the n-type substrate (12) is formed by etching on the p-type doped layer (14); an n-type doped layer (50) is formed on the sidewalls and bottom of the groove (40); the hard layer (20) is removed; p-type impurities of the p-type doped layer (14) and n-type impurities of the n-type doped layer (50) are driven in together, where the p-type impurities are diffused to form a p-type base region (60), and the n-type impurities are diffused to form an n-type buffer layer (70); a gated oxide dielectric layer (80) is formed on the surface of the groove (40); and, a polysilicon layer (90) is deposited in the groove having formed therein the gate oxide dielectric layer (80). In the method for manufacturing the injection-enhanced insulated-gate bipolar transistor, the p-type doped layer (14) and the n-type doped layer (50) are driven in together to form the p-type base region (60) and the n-type buffer layer (70), as only one drive-in process is required, production cycle is shortened in comparison with a conventional method for manufacturing the injection-enhanced insulated-gate bipolar transistor.

A trench MOSFET device includes a semiconductor layer of a first doping type. MOS transistor cells are in a body region of a second doping type in the semiconductor layer. The transistor cells include a first cell type including a first trench providing a first gate electrode or the first gate electrode is on the semiconductor surface between the first trench and a second trench, and a first source region is formed in the body region. The first gate electrode is electrically isolated from the first source region. A second cell type has a third trench providing a second gate electrode or the second gate electrode is on the semiconductor surface between the third trench and a fourth trench, and a second source region is in the body region. An electrically conductive member directly connects the second gate electrode, first source region and second source region together.

An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.