A semiconductor device according to the embodiments includes a SiC layer having a first plane, an insulating layer, and a region between the first plane and the insulating layer, the region including at least one element in the group consisting of Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), and Ba (barium), a full width at half maximum of a concentration peak of the element being equal to or less than 1 nm, and when a first area density being an area density of Si (silicon) and C (carbon) including a bond which does not bond with any of Si and C in the SiC layer at the first plane and a second area density being an area density of the element, the second area density being equal to or less than of the first area density.

A silicon carbide semiconductor device includes an impurity region including a p type impurity and disposed within a silicon carbide layer to surround an element region as seen in plan view. The impurity region has a peak concentration of the p type impurity at a position within the silicon carbide layer distant from a first main surface. The peak concentration is not less than 110.sup.16 cm.sup.3 and not more than 510.sup.17 cm.sup.3. The impurity region is formed by implanting ions of the p type impurity into the silicon carbide layer. Then, a silicon dioxide film is formed to cover the first main surface of the silicon carbide layer by performing a thermal oxidation process on the silicon carbide layer, and the concentration of the p type impurity in the vicinity of the first main surface is lowered.

A semiconductor device is provided that includes a substrate, a channel with the channel positioned on the top of the substrate, and a drift with the drift positioned on the top of the channel. The semiconductor device further includes a first poly positioned in the channel and the drift, and a second poly positioned on the top of the first poly and positioned in the drift. The first poly and the second poly are isolated by a gate oxide and a RESURF oxide, respectively, from the channel and from the drift.

There is provided a high withstand voltage LDMOS field-effect transistor that enables the compatibility of an increase of its withstand voltage and a decrease of its ON resistance. The high withstand voltage LDMOS is characterizing in including: a first electroconductive type body region formed on a main surface of a semiconductor substrate; a second electroconductive type source region formed on a surface of the body region; a second electroconductive type drift region formed so as to have contact with the body region; a second electroconductive type drain region formed on the drift region; a first electroconductive type buried region having contact with the body region and formed below the drift region; a gate electrode formed above the body region between the source region and the drift region and above the drift region nearer to the source region via a gate insulating film; a first field plate that extends from the gate electrode toward the drain region and that is formed above the drift region via a first insulating film; and a second field plate that has contact with the source region or the gate electrode and that is formed above the first field plate via a second insulating film, in which a distance between the buried region and the drain region is smaller than a distance between the first field plate and the drain region and larger than a distance between the second field plate and the drain region.

An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a drain contact on opposing sides of the epitaxial layer of the source contact, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

A semiconductor device is provided. The semiconductor device includes a first conductive type substrate; a second conductive type body region disposed in the first conductive type substrate, wherein the first conductive type is different from the second conductive type; a first conductive type first well region disposed in the second conductive type body region; a gate structure disposed over the top surface of the first conductive type substrate; a source region, wherein the source region includes a heavily-doped first conductive type source region and is disposed in the second conductive type body region; and a drain region, wherein the drain region is heavily doped first conductive type and is disposed in the first conductive type first well region.

In a plan view of a semiconductor substrate, the semiconductor substrate includes a pillar exposing area in which the pillar region is exposed on the front surface of the semiconductor substrate, a pillar contacting area in which the pillar region is in contact with a deeper side of the anode contact region, and an anode contacting area in which the anode region is in contact with the deeper side of the anode contact region. In a direction along which the pillar contacting area and the anode contacting area are aligned, a width of the pillar contacting area is smaller than a width of the anode contacting area.

A semiconductor device includes MOSFET cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region. A split gate uses the active trenches as field plates or includes planar gates between the active trenches including a MOS gate electrode (MOS gate) and a diode gate electrode (diode gate). A body region of the second conductivity type in the drift region abutts the active trenches. A source of the first conductivity type in the body region includes a first source portion proximate to the MOS gate and a second source portion proximate to the diode gate. A vertical drift region uses the drift region below the body region to provide a drain. A connector shorts the diode gate to the second source portion to provide an integrated channel diode. The MOS gate is electrically isolated from the first source portion.

A power semiconductor device includes a substrate, a main body, and an electrode unit. The main body includes an active portion disposed on the substrate, an edge termination portion, and an insulating layer disposed on the edge termination portion. The edge termination portion includes first-type semiconductor region, a second-type semiconductor region and a top surface. The first-type semiconductor region is adjacent to the active portion and has a first-type doping concentration decreased from the top surface toward the substrate. The electrode unit includes a first electrode disposed on the insulating layer, and a second electrode disposed on the substrate.

A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.