In a semiconductor integrated circuit device, a terminal cell is placed at an end of a cell row. A cell having a logical function includes: an active region including a first nanosheet extending in the X direction; and a first power line formed on the back side of a transistor and extending in the X direction. The terminal cell includes: an active region including a second nanosheet extending in the X direction; and a second power line extending in the X direction. The second nanosheet is the same in width and position in the Y direction as the first nanosheet, and the second power line is the same in width and position in the Y direction as the first power line.

In one aspect, a semiconductor device includes: a first metal layer disposed on a substrate; a dielectric layer disposed on a side of the first metal layer distant from the substrate; a second metal layer disposed on a side of the dielectric layer distant from the first metal layer, the potential of the second metal layer being higher than the potential of the first metal layer; and a metal ring disposed on a side of the dielectric layer distant from the first metal layer, the metal ring being arranged around an outer side of the second metal layer. A portion of the metal ring is located in the dielectric layer.

An integrated circuit includes a first transistor and a second transistor. A first gate spacer is along a first portion of the common gate structure, the first gate spacer having a first width. A first inner spacer is between the first semiconductor channel layers and having a second width, the first width being greater than the second width. A second gate spacer is along a second portion of the common gate structure and having a third width. A second inner spacer is between the second semiconductor channel layers and having a fourth width, and the third width is greater than the fourth width, and the second width is greater than the fourth width. An isolation structure is in contact with one end of the common gate structure, the isolation structure having a fifth width, and the fifth width is greater than the first width and the third width.

A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.

The present disclosure provides an integrated circuit (IC) structure in accordance with some embodiments. The IC structure includes a circuit structure having semiconductor devices formed on a first substrate, an interconnect structure over the semiconductor devices; and a thermal dissipation structure formed on a second substrate. The second substrate is boned to the circuit structure such that the thermal dissipation structure is interposed between the first and second substrates. The thermal dissipation structure includes a diamond-like carbon (DLC) layer. The DLC layer includes a bottom portion having large grain sizes and a top portion having fine DLC grain sizes.

A method of making a semiconductor device includes forming a first polysilicon structure over a first portion of a substrate. The method further includes forming a first spacer on a sidewall of the first polysilicon structure, wherein the first spacer has a concave corner region between an upper portion and a lower portion. The method further includes forming a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, and a difference between the first thickness and the second thickness is at most 10% of the second thickness.

A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P and NSi beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

An IC device includes isolation structures extending between two locations along a first direction in a front side of a semiconductor substrate, transistors including gates and MD segments extending between the two locations and being entireties of gates and MD segments positioned between the two locations and between the isolation structures in a second direction perpendicular to the first direction, frontside gate vias being an entirety of frontside gate vias electrically connected to the gates, and frontside S/D vias being an entirety of frontside S/D vias electrically connected to the MD segments. All of the frontside gate vias are positioned at locations of first and/or second tracks of first through third layer tracks extending in the second direction and being an entirety of lowermost frontside metal layer tracks positioned between the two locations, and all of the frontside S/D vias are positioned at locations of the second and/or third tracks.

A manufacture includes a polysilicon structure over a portion of a substrate. The manufacture further includes a spacer on a sidewall of the polysilicon structure, wherein the spacer has a concave corner region between an upper portion and a lower portion, the spacer has an outer sidewall and an inner sidewall, and the inner sidewall is between the outer sidewall and the polysilicon structure. The manufacture further includes a protective layer exposing a portion of the outer sidewall of the spacer above the concave corner region, wherein the protective layer covers an entirety of the lower portion of the spacer, and the protective layer directly contacts the substrate.