The performance of lead sulfide quantum dot (QD) photovoltaic cells is improved by exposing a QD layer to a solution containing metal salts after the synthesis of the QDs is completed. The halide ions from the salt solution passivate surface lead (Pb) sites and alkali metal ions mend Pb vacancies. Metal cations and halide anions with small ionic radius have high probability of reaching QD surfaces to eliminate surface recombination sites. Compared to control devices fabricated using only a ligand exchange procedure without salt exposure, devices with metal salt treatment show increases in both the form factor and short circuit current of the PV cell. Some embodiments comprise a method for treatment of QDs with a salt solution and ligand exchange. Other embodiments comprise a photovoltaic cell having a QD layer treated with a salt solution and ligand exchange.

Photovoltaic devices based on an Ag.sub.2ZnSn(S,Se).sub.4 (AZTSSe) absorber and techniques for formation thereof are provided. In one aspect, a method for forming a photovoltaic device includes the steps of: coating a substrate with a conductive layer; contacting the substrate with an Ag source, a Zn source, a Sn source, and at least one of a S source and a Se source under conditions sufficient to form an absorber layer on the conductive layer having Ag, Zn, Sn, and at least one of S and Se; and annealing the absorber layer. Methods of doping the AZTSSe are provided. A photovoltaic device is also provided.

This application is directed to a low cost IC solution that provides Super CMOS microelectronics macros. Hereinafter, SCMOS refers to Super CMOS and Schottky CMOS. SCMOS device solutions includes a niche circuit element, such as complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co, Ti, Ni or other metal atoms or compounds) to P- and N-Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros are composed of diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form (i) generic logic gates, (ii) functional blocks of microprocessors and microcontrollers such as but not limited to data paths, multipliers, muliplier-accumaltors, (ii) memory cells and control circuits of various types (SRAM's with single or multiple read/write port(s), binary and ternary CAM's), (iii) multiplexers, crossbar switches, switch matrices in network processors, graphics processors and other processors to implement a variety of communication protocols and algorithms of data processing engines for (iv) Analytics, (v) block-chain and encryption-based security engines (vi) Artificial Neural Networks with specific circuits to emulate or to implement a self-learning data processor similar to or derived from the neurons and synapses of human or animal brains, (vii) analog circuits and functional blocks from simple to the complicated including but not limited to power conversion, control and management either based on charge pumps or inductors, sensor signal amplifiers and conditioners, interface drivers, wireline data transceivers, oscillators and clock synthesizers with phase and/or delay locked loops, temperature monitors and controllers; all the above are built from discrete components to all grades of VLSI chips. Solar photovoltaic electricity conversion, bio-lab-on-a-chip, hyperspectral imaging (capture/sensing and processing), wireless communication with various transceiver and/or transponder circuits for ranges of frequency that extend beyond a few 100 MHz, up to multi-THz, ambient energy harvesting either mechanical vibrations or antenna-based electromagnetic are newly extended or nacent fields of the SCMOS IC applications.

Disclosed is a method of forming a CIGS-based thin film having high efficiency using a simple process at relatively low temperatures. The method includes an Ag thin film forming step and an ACIGS forming step of depositing Cu, In, Ga, and Se on the surface of the Ag thin film using a vacuum co-evaporation process. Ag, constituting the Ag thin film, is completely diffused, while Cu, In, Ga, and Se are deposited to form ACIGS together with Cu, In, Ga, and Se co-evaporated in a vacuum during the ACIGS forming step. The Ag thin film is formed and CIGS elements are then deposited using vacuum co-evaporation to form an ACIGS thin film having improved power generation efficiency at a relatively low temperature of 400 C. or less using only a single-stage vacuum co-evaporation process.

A multi-junction photovoltaic cell includes a substrate and a back contact layer formed on the substrate. A low bandgap Group IB-IIIB-VIB.sub.2 material solar absorber layer is formed on the back contact layer. A heterojunction partner layer is formed on the low bandgap solar absorber layer, to help form the bottom cell junction, and the heterojunction partner layer includes at least one layer of a high resistivity material having a resistivity of at least 100 ohms-centimeter. The high resistivity material has the formula (Zn and/or Mg)(S, Se, O, and/or OH). A conductive interconnect layer is formed above the heterojunction partner layer, and at least one additional single-junction photovoltaic cell is formed on the conductive interconnect layer, as a top cell. The top cell may have an amorphous Silicon or p-type Cadmium Selenide solar absorber layer. Cadmium Selenide may be converted from n-type to p-type with a chloride doping process.

A method for producing a P-N junction in a thin film photovoltaic cell comprising a deposition step in which are carried out successively: a layer of precursors of a photovoltaic material of type P or N, a barrier layer and a layer of precursors of a semiconducting material of type N or P, this deposition step being followed by an annealing step carried out with a supply of S and/or Se, this annealing step leading to the formation of an absorbing layer of the type P or N and of a buffer layer of type N or P and of a P-N junction at the interface between said layers.

The manufacturing method of a solar cell includes forming a photoelectric conversion unit and forming an electrode connected to the photoelectric conversion unit. The step of forming the electrode includes forming a seed formation layer connected to the photoelectric conversion unit, forming an anti-oxidation layer on the seed formation layer, performing a thermal process such that a material of the seed formation layer and a material of the photoelectric conversion unit react with each other to form a chemical bonding layer at a portion at which the seed formation layer and the photoelectric conversion unit are adjacent to each other, forming a conductive layer and a capping layer on the seed formation layer in a state in which a mask is used on the seed formation layer, and patterning the seed formation layer using either the conductive layer or the capping layer as a mask.

A hybrid all-back-contact (ABC) solar cell and method of fabricating the same. The method comprises: forming one or more patterned insulating passivation layers over at least a portion of an absorber of the solar cell; forming one or more hetero junction layers over at least a portion of the one or more patterned insulating passivation layers to provide one or more heterojunction point or line-like contacts between the one or more heterojunction layers and the absorber of the solar cell; forming one or more first metal regions over at least a portion of the one or more heterojunction layers; forming a doped region within the absorber of the solar cell; and forming one or more second metal regions over at least a portion of the doped region and contacting the doped region to provide one or more homojunction contacts.

A method for manufacturing a solar cell includes the following steps: a step in which a first electrode layer is formed on top of a substrate; a step in which a selenium-containing p-type CZTS light-absorbing layer is formed on top of the first electrode layer; a step in which the surface of the CZTS light-absorbing layer is brought into contact with an aqueous solution containing an organic sulfur compound, increasing the concentration of sulfur on the surface of the CZTS light-absorbing layer, and an n-type buffer layer is formed on top of CZTS light-absorbing layer; and a step in which a second electrode layer is formed on top of said buffer layer.

A method for forming a back contact on an absorber layer in a photovoltaic device includes forming a two dimensional material on a first substrate. An absorber layer including CuZnSnS(Se) (CZTSSe) is grown over the first substrate on the two dimensional material. A buffer layer is grown on the absorber layer on a side opposite the two dimensional material. The absorber layer is exfoliated from the two dimensional material to remove the first substrate from a backside of the absorber layer opposite the buffer layer. A back contact is deposited on the absorber layer.