The nonvolatile memory device includes a memory cell having a transistor in which an insulating isolation layer is formed in a channel region. The nonvolatile memory device includes a metal-oxide-semiconductor (MOS) transistor as a basic component. An insulating isolation layer is formed in at least a channel region, and a gate insulating layer includes an insulating layer or a variable resistor and serves as a data storage. A gate includes a metal layer formed in a lower portion thereof. First source and drain regions are lightly doped with a dopant, and second source and drain regions are heavily doped with a dopant.

The invention provides transient devices, including active and passive devices that electrically and/or physically transform upon application of at least one internal and/or external stimulus. Materials, modeling tools, manufacturing approaches, device designs and system level examples of transient electronics are provided.

A diode and a method of making same has a cathode an anode and one or more semiconductor layers disposed between the cathode and the anode. A dielectric layer is disposed between at least one of the one or more semiconductor layers and at least one of the cathode or anode, the dielectric layer having one or more openings or trenches formed therein through which the at least one of said cathode or anode projects into the at least one of the one or more semiconductor layers, wherein a ratio of a total surface area of the one or more openings or trenches formed in the dielectric layer at the at least one of the one or more semiconductor layers to a total surface area of the dielectric layer at the at least one of the one or more semiconductor layers is no greater than 0.25.

A schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 eV or more and 5.6 eV or less.

A method of manufacturing a silicon carbide semiconductor device includes a step of preparing a silicon carbide substrate having a first main surface and a second main surface located opposite to the first main surface, a step of forming a doped region in the silicon carbide substrate by doping the first main surface with an impurity, a step of forming a first protecting film on the first main surface, and a step of forming a second protecting film on the second main surface, the step of forming a first protecting film being performed after the step of forming a doped region, the method further including a step of activating the impurity included in the doped region by annealing with at least a portion of the first main surface covered with the first protecting film and at least a portion of the second main surface covered with the second protecting film.

An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers.

Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.

There is provided a silicon carbide semiconductor device allowing for integration of a transistor element and a Schottky barrier diode while avoiding reduction of an active region and decrease of a breakdown voltage. A silicon carbide semiconductor device includes a silicon carbide layer. The silicon carbide layer includes: a first region defining an outer circumference portion of an element region in which a transistor element is provided; and a JTE region provided external to the first region in a drift layer and electrically connected to the first region. The first region is provided with at least one opening through which the drift layer is exposed. The silicon carbide semiconductor device further includes a Schottky electrode provided in the opening and forming a Schottky junction with the drift layer.

A semiconductor device comprises: a semiconductor layer; and an insulating film that is formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.

A semiconductor device include a substrate, a first well region formed in the substrate, a first isolation structure formed in the first well region, a Schottky barrier structure formed on the first well region, and a plurality of assist structures formed on the first well region. The substrate includes a first conductivity type, the first well region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The assist structures physically contact the first well region.