It is an objective to improve reverse surge withstand capability of a semiconductor device, for example, a Schottky barrier diode. A p-type semiconductor section 14 includes a p+ type semiconductor portion (first concentration portion) 14a and a p type semiconductor portion (second concentration portion) 14b, which have different impurity concentrations from each other. Additionally, a part of a side surface 13S of a metal portion 13 and a part of a bottom surface 13B of the metal portion 13 connected to the side surface 13S thereof are in contact with a part of the p+ type semiconductor portion 14a. Further, at least a part of a side surface 14bS of the p type semiconductor portion 14b is in contact with a side surface 14aS of the p+ type semiconductor portion 14a.

There is provided a method of manufacturing a semiconductor device. The method of manufacturing comprises a film formation process of forming a molybdenum layer that is mainly made of molybdenum (Mo), on at least one of a semiconductor layer, an insulating film and an electrode in the semiconductor device; a heat treatment process of heating the molybdenum layer at temperature of not lower than 200 C.; and a dry etching process of processing the semiconductor device that includes the formed molybdenum layer by dry etching, subsequent to the heat treatment process.

A method of manufacturing a silicon carbide semiconductor device includes a step of preparing a silicon carbide substrate having a first main surface and a second main surface located opposite to the first main surface, a step of forming a doped region in the silicon carbide substrate by doping the first main surface with an impurity, a step of forming a first protecting film on the doped region at the first main surface, and a step of activating the impurity included in the doped region by annealing with the first protecting film having been formed, the step of forming a first protecting film including a step of disposing a material which will form the first protecting film and in which the concentration of a metal element is less than or equal to 5 g/kg on the first main surface.

In a front surface of a semiconductor base body, a gate trench is disposed penetrating an n.sup.+-type source region and a p-type base region to a second n-type drift region. In the second n-type drift region, a p-type semiconductor region is selectively disposed. Between adjacent gate trenches, a contact trench is disposed penetrating the n.sup.+-type source region and the p-type base region, and going through the second n-type drift region to the p-type semiconductor region. A source electrode embedded in the contact trench contacts the p-type semiconductor region at a bottom portion and corner portion of the contact trench, and forms a Schottky junction with the second n-type drift region at a side wall of the contact trench.

A semiconductor device of an embodiment includes a normally-off transistor having a first source electrically connected to a source terminal, a first drain, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a drain terminal, and a second gate, a capacitor having one end electrically connected to the gate terminal and the other end electrically connected to the second gate; and a first diode having a first anode electrically connected to the capacitor and the second gate and a first cathode electrically connected to the first source.

A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.

A DMOS transistor integrates a trench Schottky diode into the body contact of the transistor where the body region surrounding the Schottky metal layer forms a guard ring for the Schottky diode.

A diode having excellent switching characteristics is provided. A diode includes a silicon carbide substrate, a stop layer, a drift layer, a guard ring, a Schottky electrode, an ohmic electrode, and a surface protecting film. At a measurement temperature of 25 C., a product RQ of a forward ON resistance R of the diode and response charges Q of the diode satisfies relation of RQ0.24V.sub.blocking.sup.2. The ON resistance R is found from forward current-voltage characteristics of the diode. A reverse blocking voltage V.sub.blocking is defined as a reverse voltage which produces breakdown of the diode. The response charges Q are found by integrating a capacitance (C) obtained in reverse capacitance-voltage characteristics of the diode in a range from 0 V to V.sub.blocking.

A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.

The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer.