In one general aspect, a power rectifier device can include a drift layer including silicon carbide of n-type conductivity, and a Schottky electrode disposed on the drift layer where the Schottky electrode and a surface of the drift layer can provide a Schottky contact. The power rectifier device can also include an array of p-type regions disposed underneath the Schottky electrode.

An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p.sup.+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p.sup.+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

A semiconductor device structure according to some embodiments includes a silicon carbide substrate having a first conductivity type, a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate, and a buried junction structure in the silicon carbide drift layer. The buried junction structure has a second conductivity type opposite the first conductivity type and has a junction depth that is greater than about one micron.

Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.

In an edge termination structure portion, first and second JTE regions are disposed concentrically surrounding an active region. Between the first and second JTE regions, a p-type electric field relaxation region is disposed that includes a first subregion and a second subregion alternately and repeatedly arranged concentrically surround a periphery of the first JTE region. An average impurity concentration of the electric field relaxation region is higher that the impurity concentration of the first JTE region adjacent on the inner side and lower than the impurity concentration of the second JTE region adjacent on the outer side. First subregions have widths that decrease the farther outward they are arranged. Second subregions have widths that are substantially the same independent of position. The first subregions and the first JTE region have equal impurity concentrations. The second subregions and the second JTE region have equal impurity concentrations.

A p-type anode layer (2) is provided on an upper surface of an n-type drift layer (1). An n-type cathode layer (3) is provided on a lower surface of the n.sup.-type drift layer (1). An n-type buffer layer (4) is provided between the n.sup.-type drift layer (1) and the n-type cathode layer (3). A peak impurity concentration in the n-type buffer layer (4) is higher than that in the n.sup.-type drift layer (1) and lower than that in the n-type cathode layer (3). A gradient of carrier concentration at a connection between the n.sup.-type drift layer (1) and the n-type buffer layer (4) is 20 to 2000 cm.sup.4.

A semiconductor device according to an embodiment includes a normally-off transistor having a first drain, a first source electrically connected to a source terminal, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second gate, a second source electrically connected to the first drain, and a second drain electrically connected to a voltage terminal, a first capacitor provided between the gate terminal and the second gate, a first diode having a first anode electrically connected to the first capacitor and the second gate, and a first cathode electrically connected to the first source, a coil component provided between the voltage terminal and the second drain, and a second diode having a second anode electrically connected to the first drain and the second source, and a second cathode electrically connected to the coil component and the voltage terminal.

The disclosure concerns a device which comprises a stack of two high electron mobility transistors, referred to as first and second transistor, separated by an insulating layer and each provided with a stack of semiconductor layers respectively referred to as first stack and second stack, the first and the second stack each comprising, from the insulating layer to, respectively, a first and a second surface, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first set of electrodes and a second set of electrodes, the first and the second set of electrodes each comprising a source electrode, a drain electrode, and a gate electrode which are arranged so that the first and the second transistor are electrically connected head-to-tail.

The disclosure concerns a device which comprises a stack of two high electron mobility transistors, referred to as first and second transistor, separated by an insulating layer and each provided with a stack of semiconductor layers respectively referred to as first stack and second stack, the first and the second stack each comprising, from the insulating layer to, respectively, a first and a second surface, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first set of electrodes and a second set of electrodes, the first and the second set of electrodes each comprising a source electrode, a drain electrode, and a gate electrode which are arranged so that the first and the second transistor are electrically connected head-to-tail.

In a semiconductor device according to the technology disclosed in the present specification, a temperature detection region is provided with a diffusion layer of a second conductivity type provided on a surface layer of a drift layer of a first conductivity type, a well layer of a first conductivity type provided on a surface layer of the diffusion layer and electrically connected to an anode electrode, and a cathode layer of a first conductivity type provided on a surface layer of the well layer and electrically connected to a cathode electrode.