The invention provides a Schottky diode structure. An exemplary embodiment of a Schottky diode structure includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed on the first well region. A first electrode is disposed on the active region, covering the first doped region. A second electrode is disposed on the active region, contacting to the first well region. A gate structure is disposed on the first well region. A second doped region, having a second conductive type opposite to the first conductive type, and is formed on the first well region. The gate structure and the second doped region are disposed between the first and second electrodes.

A semiconductor device includes a semiconductor body including first and second lateral surfaces. A first device region includes a drift region of a first conductivity type, and a drift current control region of a second conductivity type being spaced apart from the second lateral surface by the drift region. A second device region includes a barrier layer, and a buffer layer having a different band gap than the barrier layer so that a two-dimensional charge carrier gas channel arises along an interface between the buffer layer and the barrier layer. An electrically conductive substrate contact forms a low ohmic connection between the two-dimensional charge carrier gas channel and the drift region. A gate structure is configured to control a conduction state of the two-dimensional charge carrier gas. The drift current control region is configured to block a vertical current in the drift region via a space-charge region.

A semiconductor device includes: a semiconductor substrate including a trench provided in a surface of the semiconductor substrate; a trench electrode provided in the trench; an interlayer insulating film covering a surface of the trench electrode and protruding from the surface of the semiconductor substrate; a Schottky electrode provided on the surface of the semiconductor substrate, provided in a position separated from the interlayer insulating film, and being in Schottky contact with the semiconductor substrate; an embedded electrode provided in a concave portion between the interlayer insulating film and the Schottky electrode and made of a metal different from a metal of the Schottky electrode; and a surface electrode covering the interlayer insulating film, the embedded electrode, and the Schottky electrode.

A semiconductor device includes at least one highly doped region of an electrical device arrangement formed in a semiconductor substrate and a contact structure including an NTC (negative temperature coefficient of resistance) portion arranged adjacent to the at least one highly doped region at a front side surface of the semiconductor substrate. The NTC portion includes a negative temperature coefficient of resistance material.

A semiconductor device includes a semiconductor body including first and second lateral surfaces. A first device region includes a drift region of a first conductivity type, and a drift current control region of a second conductivity type being spaced apart from the second lateral surface by the drift region. A second device region includes a barrier layer, and a buffer layer having a different band gap than the barrier layer so that a two-dimensional charge carrier gas channel arises along an interface between the buffer layer and the barrier layer. An electrically conductive substrate contact forms a low ohmic connection between the two-dimensional charge carrier gas channel and the drift region. A gate structure is configured to control a conduction state of the two-dimensional charge carrier gas. The drift current control region is configured to block a vertical current in the drift region via a space-charge region.

A power converter module includes a baseplate, a substrate on the baseplate, one or more silicon carbide switching components on the substrate, and a housing over the baseplate, the substrate, and the one or more silicon carbide switching components. The housing has a footprint less than 25 cm.sup.2. Including a baseplate in a power converter module with a footprint less than 25 cm.sup.2 runs counter to accepted design principles for silicon and silicon carbide-based power converter modules, but may improve performance of the power converter module and/or decrease the cost of the power converter module.

A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned dielectric layer atop the Kelvin-contact source and the trench gate; a patterned top metal layer. As a result: a planar ledge is formed atop the Kelvin-contact source; the MOSFET device exhibits a lowered body Kelvin contact impedance and, owing to the presence of the planar ledge, a source Kelvin contact impedance that is lower than an otherwise MOSFET device without the planar ledge; and an integral parallel Schottky diode is also formed.

An integrated circuit and method with a metal gate transistor and with a Schottky diode where the metal used to form the Schottky diode is the metal used to form the metal gate.

At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.

A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.