Provided is a logic circuit including a first circuit including a static D flip-flop and a second circuit including a dynamic D flip-flop. The first circuit receives a clock signal and a first reset signal. The first circuit outputs a second reset signal generated by synchronizing the first reset signal with the clock signal. The second circuit receives the clock signal and a signal based on the second reset signal.

Provided are a pixel array and an image sensor including the same. The pixel array includes a plurality of sub-pixels adjacent to each other and a readout circuit connected to the plurality of sub-pixels through a floating diffusion node. Each of the sub-pixels includes a photoelectric conversion element, an overflow transistor connected to the photoelectric conversion element, a phototransistor connected to the photoelectric conversion element and the overflow transistor, and a storage element connected to the phototransistor.

An image sensor includes a pixel array; a logic circuit configured to convert an image signal generated from the pixel array during a first period into image data; and a memory. The image data may be written in the memory during a second period, of which at least a portion overlaps the first period. The logic circuit may write dummy data in the memory during a third period overlapping the first period and not overlapping the second period.

There is provided a pixel circuit including a first circuit and a second circuit. The first circuit is used to output a first voltage associated with exposure intensity. The second circuit is used to output a second voltage associated with exposure time interval. The processor multiples the first voltage to a ratio between a reference voltage and the second voltage to obtain an actual light intensity, wherein the reference voltage is a voltage value outputted by the second circuit of a dummy pixel.

A device uses gated retro-reflectors to transmit uplink data in a visible light communication (VLC) system. The gated retro-reflector includes a retro-reflector and a gating shutter between the retro-reflector and a VLC light source. A light sensor receives VLC data at regular intervals in which a light pulse received during one of the intervals represents a first downloaded symbol and absence of a light pulse during another one of the intervals represents a second downloaded symbol. A controller controls the gating shutter to send uplink data from the device responsive to each received VLC light pulse. The controller opens the gating shutter during the reception of a VLC light pulse to upload a first uploaded symbol and closes the gating shutter during the reception of a VLC light pulse to upload a second uploaded symbol.

There is provided a solid-state image sensor including a pixel circuit including a plurality of pixels and imaging a subject, a peripheral circuit provided in a vicinity of the pixel circuit and performing operation in regard to imaging, and a connection element electrically connecting, in initialization of the pixels, elements in the pixels to which a predetermined voltage is applied for initializing the pixels to the peripheral circuit with the predetermined voltage.

A dual mode image sensor is provided. The image sensor includes an on-chip sensing array, on-chip analog-to-digital converters, and an on-chip processor. The sensor array has rows and columns of discrete sensor elements. The dual mode image sensor has a scene sensing mode and an image capture mode, which use the same set of imaging optics. The processor includes a dual context register; one being for the scene sensing mode and the other for image capture mode. The scene sensing mode is configured to output results of object sensing, motion detection, focus evaluation and illumination measurement to the analog-to-digital converters. The image capture mode is configured to output captured images to the analog-to-digital converters, which are configured to send the digital data to the processor. The processor is configured to switch from scene sensing mode to image capture mode based upon the scene sensing mode output results.

A CMOS image sensor for a camera assembly is provided, having a sensor die with opposing faces, an upper face, and a lower face. On the upper face, the sensor die is provided with a sensor array, an analog-to-digital conversion module, a digital logic circuit, and a timing and clock control circuit. The sensor array is substantially centered on the sensor die. The analog-to-digital conversion module is split into two submodules. Each submodule is disposed adjacent to the sensor array and positioned on opposing sides of the sensor array. The digital logic circuit forms a first row. The timing and clock control circuit and the analog signal processing circuit are adjacent and form a second row. The first and second rows have similar dimensions and are disposed on opposite sides of the sensor array.

A solid-state imaging device includes a first chip including a plurality of pixels, each pixel including a light sensing unit generating a signal charge responsive to an amount of received light, and a plurality of MOS transistors reading the signal charge generated by the light sensing unit and outputting the read signal charge as a pixel signal, a second chip including a plurality of pixel drive circuits supplying desired drive pulses to pixels, the second chip being laminated beneath the first chip in a manner such that the pixel drive circuits are arranged beneath the pixels formed in the first chip to drive the pixels, and a connection unit for electrically connecting the pixels to the pixel drive circuits arranged beneath the pixels.

A solid-state imaging device includes a photodetecting section, a vertical shift register section, first row selection lines, and second row selection lines. The vertical shift register section provides the row selection lines of the m-th row with common row selection signals.