A dual-column-parallel image CCD sensor utilizes a dual-column-parallel readout circuit including two pairs of cross-connected transfer gates to alternately transfer pixel data (charges) from a pair of adjacent pixel columns to a shared output circuit at high speed with low noise. Charges transferred along the two adjacent pixel columns at a line clock rate are alternately passed by the transfer gates to a summing gate that is operated at twice the line clock rate to pass the image charges to the shared output circuit. A symmetrical Y-shaped diffusion is utilized in one embodiment to merge the image charges from the two pixel columns. A method of driving the dual-column-parallel CCD sensor with line clock synchronization is also described. A method of inspecting a sample using the dual-column-parallel CCD sensor is also described.

Read electrodes are provided to drain signal charge of pixels from photoelectric conversion units provided in the pixels separately to a vertical transfer unit. During a first exposure period during which an object is illuminated with infrared light, signal charge obtained from a first pixel, and signal charge obtained from a second pixel adjacent to the first pixel, are added together in the vertical transfer unit to produce first signal charge. During a second exposure period during which the object is not illuminated with infrared light, signal charge obtained from the first pixel, and signal charge obtained from the second pixel adjacent to the first pixel, are transferred without being added to the first signal charge in the vertical transfer unit, and are added together in another packet to produce second signal charge.

An image processing apparatus to execute noise reduction processing on image data includes a setting unit, a determination unit, and an output unit. The setting unit sets a pixel group from among a plurality of pixel group candidates. The plurality of pixel group candidates includes at least a first pixel group having a plurality of pixels being a first number of pixels or a second pixel group having a plurality of pixels being a second number of pixels which is different from the first number of pixels. The determination unit determines, based on a similarity between a target pixel and a reference pixel that is obtained according to the set pixel group, a weight corresponding to the reference pixel. The output unit outputs a value, calculated based on a pixel value of the reference pixel and the weight, as a noise-reduced pixel value of the target pixel.

An electronic device disclosed herein includes a photodiode, and a plurality of storage components each configured to independently sample and hold charges from the photodiode during each of a plurality of integration periods without discharging the held charge between successive integration periods of the plurality thereof. Each storage component accumulates the charges from the photodiode for a given time window during each integration period, with the given time window for each storage component being different than the given time window for each other storage component. Readout circuitry is configured to transfer the charges from each storage component to a readout node in a respective read period for that storage component. The photodiodes and storage components are not configured to be reset between successive time windows during each integration period.

An endoscope system includes an image pickup section provided with an image sensor and configured to obtain an examination image; a cable that transmits the examination image; and a processor that receives the examination image, performs image processing, and displays the processed image. The processor includes: a cable driver that applies a voltage higher than an input voltage standard of the image pickup section so as to compensate for attenuation of a high-frequency signal caused by the cable and outputs a clock signal for driving the image pickup section; a peaking circuit that performs waveform correction of the clock signal; and a DC level limiting circuit configured to limit, when a clock signal inputted from the first peaking circuit is switched to a DC voltage, an amplitude level of the DC voltage so as not to exceed a level of the input voltage standard of the image pickup section.

Image capturing systems with interline CCD structures designed to reduce the delay between captures of subsequent image frames are disclosed. Proposed interline CCD structures include two or more sets of storage units associated with a given set of photodetecting elements, where each photodetecting element is associated with one storage unit of each set of storage units in that the charge generated by the photodetecting element during the acquisition of a particular image frame (i.e. during a particular exposure period) may be stored any one of these storage units prior to read-out. Providing multiple sets of storage units allows read-out of charge corresponding to one image frame and stored in one set of storage units while accumulating charge corresponding to another image frame in another set of storage units, thus reducing the delay between captures of different image frames. Consequently, errors and artifacts of the image capturing system can be minimized.

An array sensor and a method for forming and operating the same are provided. The array sensor includes: a sensor circuit including an array of pixel units that includes N rows of pixel units; and a driving circuit including at least N rows of shifting units; where the driving circuit further includes: a first global clearing signal line connected with odd rows of shifting units, a signal of which being applied to trigger the odd rows of shifting units to simultaneously turn on odd rows of pixel units, so that the odd rows of pixel units simultaneously discharge residual charge; and a second global clearing signal line connected with even rows of shifting units, a signal of which being applied to trigger the even rows of shifting units to simultaneously turn on even rows of pixel units, so that the even rows of pixel units simultaneously discharge residual charge.

A high dynamic range imaging pixel may include a photodiode that generates charge in response to incident light. When the generated charge exceeds a first charge level, the charge may overflow through a first transistor to a first storage capacitor. When the generated charge exceeds a second charge level that is higher than the first charge level, the charge may overflow through a second transistor. The charge that overflows through the second transistor may alternately be coupled to a voltage supply and drained or transferred to a second storage capacitor for subsequent readout. Diverting more overflow charge to the voltage supply may increase the dynamic range of the pixel. The amount of charge diverted to the voltage supply may therefore be updated to control the dynamic range of the imaging pixel.

A solid state imaging device has: a photosensitive part containing a plurality of charge transfer parts that transfer, in column units, the signal charges of a plurality of photoelectric conversion elements disposed in a matrix; a conversion/output unit that converts, to an electrical signal, the signal charges forwarded by the charge transfer parts; a peripheral circuit part that performs a predetermined process with respect to the electrical signals from the conversion/output part; a relay part that relays the forwarding to the peripheral circuit part of the electrical signal from the conversion/output part; a first substrate where a photosensitive part and the conversion/output part are formed; and a second substrate where the peripheral circuit part is formed. The first and second substrates are stacked together, and the relay part electrically connects the conversion/output part formed at the first substrate to the peripheral circuit part formed at the second substrate.

In time-delay-and-integrate (TDI) imaging, a charge-couple device (CCD) integrates and transfers charge across its columns. Unfortunately, the limited well depth of the CCD limits the dynamic range of the resulting image. Fortunately, TDI imaging can be implemented with a digital focal plane array (DFPA) that includes a detector, analog-to-digital converter (ADC), and counter in each pixel and transfer circuitry connected adjacent pixels. During each integration period in the TDI scan, each detector in the DFPA generates a photocurrent that the corresponding ADC turns into digital pulses, which the corresponding counter counts. Between integration periods, the DFPA transfers the counts from one column to the next, just like in a TDI CCD. The DFPA also non-destructively transfers some or all of the counts to a separate memory. A processor uses these counts to estimate photon flux and correct any rollovers caused by “saturation” of the counters.