Patent classifications
H04N5/355
CTIA CMOS IMAGE SENSOR PIXEL WITH ZERO-BIASED MULTIPLEXER
An image sensor and pixel circuit therefor includes a plurality of photoelectric conversion devices, a zero-biased multiplexer connected to the plurality of photoelectric conversion devices, an amplifier including a first input terminal connected to the zero-biased multiplexer, and an output terminal, a capacitor disposed between the first input terminal and the output terminal, and a reset switch disposed between the first input terminal and the output terminal in parallel with the capacitor, the reset switch including a body terminal connected to a common reference voltage.
SOLID-STATE IMAGING DEVICE AND IMAGING APPARATUS
A solid-state imaging device includes: a photoelectric conversion element that is disposed on a semiconductor substrate and generates signal charges by photoelectric conversion; a first diffusion layer that holds signal charges transferred from the photoelectric conversion element; a capacitive element that holds signal charges overflowing from the photoelectric conversion element; an amplifier transistor that outputs a signal according to the signal charges in the first diffusion layer; a first contact that is connected to the first diffusion layer; a second contact that is connected to a gate of the amplifier transistor; and a first wire that connects the first contact and the second contact. A shortest distance between the semiconductor substrate and the first wire is less than a shortest distance between the semiconductor substrate and the capacitive element.
SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE
The present disclosure relates to a solid-state imaging device that makes it possible to suppress deterioration of phase difference information, and an electronic device.
There is provided a solid-state imaging device including a pixel array unit in which a plurality of pixels is two-dimensionally arrayed. The plurality of pixels includes a phase difference pixel for phase difference detection, the pixel array unit has an array pattern in which pixel units including neighboring pixels of a same color are regularly arrayed, and the phase difference pixel is partially not added when horizontal/vertical addition is performed on a pixel signal of a predetermined pixel in a horizontal direction and a pixel signal of a predetermined pixel in a vertical direction, in reading the plurality of pixels. The present disclosure can be applied to, for example, a CMOS image sensor having a phase difference pixel.
IMAGING DEVICE
An imaging device capable of taking an image in both a dark environment and a bright environment in a light amount range equivalent to or greater than that of human vision is desired. A wide dynamic range and high image quality are achieved. In order to obtain an image with a widened dynamic range, two capacitors, a large capacitor and a small capacitor, are provided in one pixel. The large capacitor is formed to be interposed between a transistor for controlling the amount of charge overflowed from the small capacitor and a transistor for resetting accumulated charge, and OS transistors are used as these two transistors. The OS transistor has extremely low off-state current characteristics, and thus can widen the dynamic range of imaging.
HDR IMAGE SENSOR EMPLOYING MULTI-TAP PIXEL ARCHITECTURE AND METHOD FOR OPERATING SAME
An image sensor may include control circuitry, a plurality of pixels, and an image processor. Each pixel includes a photodetector, at least first and second storage nodes, and transfer circuitry. The transfer circuitry is responsive to control signals generated by the control circuitry to transfer first charges generated by the photodetector during a first exposure time within a frame period to the first storage node. Second charges may be generated by the photodetector during a second, longer exposure time during the frame period, and transferred to the second storage node. The image processor may generate image frame data based on output voltage samples derived from the first and second charges of each of the plurality of pixels.
Simulated rolling shutter image data
A system for converting global shutter image data into simulated rolling shutter image data may include a global-to-rolling shutter image converter. The converter may be configured to receive global shutter image data associated with a plurality of global shutter images. The global shutter image data may include dynamic global shutter image data representative of a moving object in the plurality of global shutter images. The converter may also be configured to determine an optical flow field based at least in part on two or more of the plurality of global shutter images and generate the simulated rolling shutter image based at least in part on the optical flow field. The converter may also be configured to generate high dynamic range (HDR) images based at least in part on the optical flow field and the global shutter image data.
Image sensor including DRAM capacitor and operating method thereof
An image sensor includes a pixel array having a plurality of pixels; a row driver providing the pixel array with a boosting signal; and a read-out circuit configured to read out pixel signals output from pixels of a row line selected by the row driver. Each of the plurality of pixels includes: a first photodiode; a transmission transistor connected to the first photodiode; a first floating diffusion node, a second floating diffusion node, and a third floating diffusion node, which are connected to the transmission transistor to accumulate charges generated by the first photodiode; an LCG capacitor connected to the third floating diffusion node to accumulate the charges generated by the first photodiode; an MCG transistor connected between the first floating diffusion node and the second floating diffusion node; and an LCG transistor connected to the third floating diffusion node.
Imaging device and imaging system
In an imaging device according to the present disclosure, during a period in which a signal from an amplifier transistor is output from a pixel via a select transistor, the gate voltage of the capacitance addition transistor changes frons the first voltage VH to the second voltage VL, and the amount of voltage change per time until the gate voltage changes from the first voltage VH to the second voltage VL is smaller than the amount of voltage change per unit time until the gate voltage changes from the second voltage VL to the first voltage VH.
Methods and apparatus for true high dynamic range imaging
When imaging bright objects, a conventional detector array can saturate, making it difficult to produce an image with a dynamic range that equals the scene's dynamic range. Conversely, a digital focal plane array (DFPA) with one or more m-bit counters can produce an image whose dynamic range is greater than the native dynamic range. In one example, the DFPA acquires a first image over a relatively brief integration period at a relatively low gain setting. The DFPA then acquires a second image over longer integration period and/or a higher gain setting. During this second integration period, counters may roll over, possibly several times, to capture a residue modulus 2.sup.m of the number of counts (as opposed to the actual number of counts). A processor in or coupled to the DFPA generates a high-dynamic range image based on the first image and the residues modulus 2.sup.m.
Split-readout image sensor
First and second readout circuits, each having a respective floating diffusion node, are coupled to a photodetection element within a pixel of an integrated-circuit image sensor. Following an exposure interval in which photocharge is accumulated within the photodetection element, a first portion of the accumulated photocharge is transferred from the photodetection element to the first floating diffusion node to enable generation of a first output signal within the first readout circuit, and a second portion of the accumulated photocharge is transferred from the photodetection element to the second floating diffusion node to enable generation of a second output signal within the second readout circuit. A digital pixel value is generated based on the first and second output signals.