A coherent imaging system including a transmitter and a receiver. The transmitter includes a coherent source and a power splitter for splitting the electromagnetic radiation into a reference and a signal beam. The receiver includes an image forming device and an array of pixels. Each of the pixels include means for collecting at least a portion of the signal beam imaged on the pixel by an image forming device, as a collected signal; means for splitting the collected signal into a plurality of collected signals each having different phase shifts; means for mixing each of the collected signals with the reference beam so as to form a plurality of mixed signals; and means for detecting the mixed signals and outputting a plurality of output electrical signals in response to the mixed signals.

Provided herein may be an image sensing device and a method of operating the same. An image sensing device may include an image sensor obtaining an image using a plurality of pixels, and an image processor configured to use pixel values included in a region of interest included in the image to generate a gain table including gain table values corresponding to a first resolution, convert the gain table into a target table including target table values corresponding to a second resolution which is lower than the first resolution, and cancel noise included in the image based on the target table.

A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.

The present technology relates to an imaging device of global shutter type, and relates to an imaging device and electronic equipment capable of inhibiting interference between a photoelectric conversion unit and an element that holds charge that has been transferred from the photoelectric conversion unit. An imaging device includes, in a pixel: a photoelectric conversion unit; a charge transfer unit; an electrode that is used to transfer charge from the photoelectric conversion unit to the charge transfer unit; a charge-voltage conversion unit; and a charge drain unit. Here, the charge transfer unit is allowed to transfer charge in a first transfer direction to the charge-voltage conversion unit and a second transfer direction to the charge drain unit. The present technology can be applied to, for example, a CMOS image sensor of global shutter type.

An imaging device 100 includes a pixel array PA. A first period, a third period, and a second period appear in this order in one frame. During the first period, pixel signal readout is performed on at least one first row in the pixel array PA. During the second period, pixel signal readout is performed on at least one second row in the pixel array PA. At least one of the at least one first row or the at least one second row includes two rows in the pixel array PA. During the third period, no pixel signal readout is performed on the rows in the pixel array PA. Each of the first period and the second period is one of the high-sensitivity exposure period and the low-sensitivity exposure period. The third period is the other of the high-sensitivity exposure period and the low-sensitivity exposure period.

An imaging apparatus includes a first photoelectric conversion unit configured to convert light into charge, a second photoelectric conversion unit configured to convert light into charge, and a comparison unit. The comparison unit includes a first transistor and a second transistor. The first transistor receives a signal that is based on the charge converted by the first photoelectric conversion unit. The second transistor receives a signal that is based on the charge converted by the second photoelectric conversion unit.

An image sensor includes a dual conversion gain pixel to output a high conversion gain signal according to a high conversion gain and output a low conversion gain signal according to a low conversion gain, by adjusting a conversion gain; a scaler to scale a voltage level of the high conversion gain signal; a ramp generator to generate a first ramp signal and a second ramp signal, slopes of the first and second ramp signals being different from each other; a comparator to compare the scaled high conversion gain signal and the first ramp signal to output a first comparison result, and compare the low conversion gain signal and the second ramp signal to output a second comparison result; and a counter to output a first counting result value based on the first comparison result and output a second counting result value based on the second comparison result.

An imaging element of the present disclosure includes an analog-to-digital converter configured to convert multiple analog pixel signals that are acquired under multiple imaging conditions different from each other and that are output from a pixel, to multiple digital pixel signals, a threshold setting unit configured to set, on an input side of the analog-to-digital converter, a threshold that is randomly varied, a comparison unit configured to use, as a comparison threshold, the threshold set by the threshold setting unit and compare the comparison threshold with one of the multiple analog pixel signals, and a selection unit configured to select and output, on the basis of a result of comparison from the comparison unit, one of the multiple digital pixel signals that are output from the analog-to-digital converter.

An imaging device including: a first semiconductor substrate; a second semiconductor substrate; and a wiring layer. The first semiconductor substrate has a first surface and a second surface and includes a sensor pixel. The second semiconductor substrate has a third surface and a fourth surface and includes a readout circuit that outputs a pixel signal based on an output from the sensor pixel. The second semiconductor substrate is stacked on the first semiconductor substrate with the first surface and the fourth surface opposed to each other. The wiring layer is between the first semiconductor substrate and the second semiconductor substrate and includes a first wiring line and a second wiring line that are electrically coupled to each other. One of the first wiring line and the second wiring line is in an electrically floating state while the other is electrically coupled to a transistor.

Provided is an image sensor including a first layer including a first semiconductor substrate including a pixel unit in which a plurality of unit pixels are provided, and a first wiring layer provided on the first semiconductor substrate, a second layer including a second semiconductor substrate on which a plurality of transistors configured to operate a global shutter operation are provided, and a second wiring layer provided on the second semiconductor substrate, and provided on the first layer such that the first wiring layer and the second wiring layer oppose each other in a first direction, a plurality of first bonding structures bonding the first layer to the second layer based on a first bonding metal exposed on a surface of the first wiring layer being in contact with a second bonding metal exposed on a surface of the second wiring layer, a third layer including a third semiconductor substrate on which a logic circuit is provided, and a third wiring layer provided on the third semiconductor substrate, and bonded to the second layer such that the second semiconductor substrate and the third wiring layer oppose each other in the first direction, and a plurality of second bonding structures extending from the second wiring layer, and bonding the second layer to the third layer based on a bonding via penetrating the second semiconductor substrate being in contact with a third bonding metal exposed to a surface of the third wiring layer.