An emulation environment includes a host system and an emulator. The host system configures the emulator to emulate a design under test (DUT) and the emulator emulates the DUT accordingly. During emulation, the emulator traces limited signals of the DUT and stores values of the traced signals. When values of certain signals of the DUT are needed for analysis or verification of the DUT but the signals were not traced by the emulator, the host system simulates one or more sections of the DUT to obtain values of the signals. Signals traced by the emulator are used as inputs to simulate the one or more sections.

Various techniques are provided to implement a logical memory in programmable logic devices (PLDs) having embedded block RAMs (EBRs). For example, a computer-implemented method includes determining a main area of a logical memory that can be fully mapped to a first one or more EBRs configured in a first depth-width configuration, mapping the main area to the first one or more EBRs, and mapping the remainder of the logical memory to a second one or more EBRs configured in a second or more depth-width configurations. The mapping of the remainder of the logical memory may be performed hierarchically by a recursive process, in some embodiments. The depth-width configurations and the corresponding mapping may be selected according to an efficiency metric, for example. Other embodiments include a system comprising a PLD and a configuration memory storing configuration data generated by such a method, and a PLD configured with such configuration data.

Embodiments include a computer implemented method comprising: while designing a chip, identifying a plurality of partitions in the chip, for a first partition of the plurality of partitions in the chip, identifying a plurality of pins configured to interconnect the first partition with one or more other partitions of the plurality of partitions of the chip, assigning a name to each of the plurality of pins associated with the first partition of the plurality of partitions, based on the names assigned to each of the plurality of pins, forming a plurality of groups such that each group of the plurality of groups is associated with a corresponding one or more pins of the plurality of pins, and based on forming the plurality of groups, designing a first subset of the plurality of pins to be located at close proximity in the chip.

An in-ground geothermal heat pump (GHP) closed loop design program is disclosed for designing, analyzing, and simulating a detailed model and analysis of a building's in-ground geothermal heat pump system, including borehole length, number of boreholes, heat pump capacity, grid layout, total electric operating costs, efficiency ratios, and hybrid designs, among others. In one aspect of the disclosure described herein, the GHP design program can reliably and efficiently predict the fluctuations of the GHP equipment performance in very small increments which enable the determination of energy consumption and demand information on a specific and unique hourly schedule basis for the building design, including incorporating thermal load data for each individual zone of the building. More specifically, the small increment method here can be used to eliminate overly broad approximations by evaluating GHP performance that is specific to building dynamics, constants, and variables for all of the building individual zones and the building's hourly operating schedule, thereby providing an efficient, reliable, simple, and effective geothermal heat pump design and simulation model.

Disclosed is an approach to implement a requirements-driven analog verification flow. Disparate islands of verification tasks are performed with individual cellviews to be set into an overarching and closed loop verification flow context for a project or a complex verification task.

Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes.

Certain examples described herein provide a representation of a three-dimensional object for production of said object. These examples use a material volume coverage representation that is generated from received object data, such as a vector object representation. The material volume coverage representation includes material volume coverage vectors for at least volumes forming part of a raster representation of the three-dimensional object. The raster representation is generated from the vector representation. Each material volume coverage vector represents a probabilistic distribution of materials available to the apparatus for production of the three-dimensional object and combinations of said materials.

The present invention relates to a method of dental implant treatment planning, a device and a recording medium therefore. The device for dental implant treatment planning according to the present invention can move or rotate the grouped objects together in 2D or 3D model about teeth arrangement for implant treatment planning with grouping function of the implant objects. So, it decreases complexity of manipulation of the implant objects, provides users with convenience to easily modify position or size of the implant objects, and improves the accuracy of the modification.

A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.

Embodiments of the present invention simulate a real-world system by first generating a time dependent system of equations that represents the real-world system where the time dependent system of equations has a defined constraint. Next, the constraint is de-coupled from the time-dependent system of equations using a matrix representing an approximation of physics of the real-world system, the de-coupling generating a first system of equations representing the constraint and a second system of equations representing physics of the real-world system. In turn, the generated first and second systems of equations are solved and the real-world system is automatically simulated by generating a simulation using results from solving the first and second systems of equations.