A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.

A method of designing a semiconductor device and system for designing a semiconductor device are provided. The method of designing a semiconductor device includes providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; placing the first and second active fins in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout.

A NoC timing power estimating method includes: estimating a plurality of transmission timing of a plurality of transmission units of at least a packet, the transmission timing indicating respective time points at which the transmission units enter/leave a plurality of passing elements of the NoC; based on the transmission timing of the transmission units, estimating respective circuit states and respective power states of the passing elements of the NoC, the circuit state indicating an operation state of the passing element and the power state being related to the circuit state; and based on the power states of the passing elements of the NoC, estimating power consumption of the NoC.

Disclosed is a shaped horn in conjunction with a dielectric tube for enhanced aperture directivity that can achieve a near optimum efficiency. The shaped horn provides additional mode control to provide an improved off-axis cross-polarization response. The horn shape can be individually optimized for isolated horns or for horns in a feed array. The feed array environment can produce results that lead to a different optimized shape than the isolated horn. Lower off axis cross-polarization can result in improved efficiency and susceptibility to interference.

A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process is provided. The process includes: generating a second characteristic model from a plurality of first characteristic models by using a maximum value and a minimum value of a prescribed parameter in the plurality of first characteristic models; executing simulation by using the second characteristic model; calculating a plurality of first margins for an evaluation item according to a result of the simulation; calculating a plurality of second margins for the evaluation item with respect to each of the first characteristic models; calculating a ratio of each of the plurality of second margins to a maximum margin of the plurality at first margins; and ranking the plurality of first characteristic models according to the ratio.

A method for operating a machine component under stress. The method comprises determining a probability of failure PoF(N) of the component as a function of N cycles, selecting a time-based acceptable risk limit for the component and selecting an operational profile for the component, converting the time-based acceptable risk limit to a cycle-based acceptable risk limit using the operational profile, comparing the cycle-based acceptable risk limit with the PoF(N) values to determine an operational status of the component, comparing the cycle-based acceptable risk limit with the PoF(N) values, and operating the machine component responsive to results of the comparing step.

Methods and systems of an electronic circuit design system described herein provide a new layout editor tool to make edits in an electronic circuit layout. A plurality of partitions is created in the electronic circuit layout. The new layout editor tool enables multiple electronic circuit designers to edit a different partition of the plurality of partitions of the same electronic circuit layout at the same time and save the edited partition locally.

A method for generating production code from a block diagram in a technical computing environment on a host computer. A first block receives a first input signal that has a plurality of elements. A size of a first required signal of the external function is determined and compared to a size of the first input signal. When the size of the first required signal corresponds to the size of an element in the first input signal a production code is generated enclosing a call of the external function by a loop consecutively addressing each of the plurality of elements in the first input signal. When the size of the first required signal corresponds to the size of the first input signal a production code is generated having a call of the external function without enclosing loop over the elements in the first input signal.

Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program, and a method for behavioral modeling of jitters due to power supply noise for input/output (I/O) buffers. The method may include accessing physical model data describing a physical structure of an integrated circuit device, and accessing a behavioral model schema for evaluating electrical characteristics of the integrated circuit device including jitter effects introduced by power noise in the integrated circuit device. The method may further include generating behavioral model data based on the physical model data, the behavioral model data including the electrical characteristics of integrated circuit device. The method may further include providing a data file including the behavioral model data.

Approaches for processing a circuit design include determining pin slack values for pins of the circuit elements in the circuit design. A processor selects a subset of endpoints based on pin slack values of the endpoints being in a critical slack range and determines startpoints of the circuit design that are in respective critical fanin cones. For each endpoint of the subset, the processor determines an arrival time from each startpoint in the respective critical fanin cone and determines for each startpoint-endpoint pair, a respective set of constraint values as a function of the respective arrival time from the startpoint. The processor generates a graph in the memory circuit from the startpoint-endpoint pairs. First nodes in the graph represent the startpoints and second nodes in the graph represent the endpoints, and values in the respective set of constraint values are associated with edges that connect the nodes.