An integrated circuit includes user storage circuits, a local control circuit, and scan storage circuits arranged in a scan chain. At least a portion of a design-under-test is implemented in a subset of the integrated circuit that comprises the user storage circuits. The local control circuit retrieves data stored in the user storage circuits through the scan storage circuits without erasing the data stored in the user storage circuits after halting oscillations in a user clock signal that clocks the user storage circuits. The local control circuit restarts oscillations in the user clock signal after the data is provided from the user storage circuits to the scan storage circuits.

An integrated device product having objects positioned in accordance with in-situ constraints. Said in-situ constraints comprise predetermined constraints and their local modifications. These local modifications, individually formulated for a specific pair of objects, account for on-the-spot conditions that influence the optimal positioning of the objects. The present invention improves the yield of integrated devices by adding local process modification distances to the predetermined constraints around processing hotspots thus adding extra safety margin to the device yield.

A method of constructing an RF filter comprises designing an RF filter that includes a plurality of resonant elements disposed, a plurality of non-resonant elements coupling the resonant elements together to form a stop band having a plurality of transmission zeroes corresponding to respective frequencies of the resonant elements, and a sub-band between the transmission zeroes. The non-resonant elements comprise a variable non-resonant element for selectively introducing a reflection zero within the stop band to create a pass band in the sub-band. The method further comprises changing the order in which the resonant elements are disposed along the signal transmission path to create a plurality of filter solutions, computing a performance parameter for each of the filter solutions, comparing the performance parameters to each other, selecting one of the filter solutions based on the comparison of the computed performance parameters, and constructing the RF filter using the selected filter solution.

A system for monitoring the condition of elongate structural elements, for example, railway rails, and a method of designing and manufacturing the system is disclosed. The method includes identifying and selecting suitable modes of propagation and signal frequencies that can be expected to travel large distances through an elongate structural element; designing a transducer that will excite the selected mode at the selected frequency; numerically modelling the transducer as attached to the elongate structural element; validating the transducer design by analysing a harmonic response of the selected mode of propagation to excitation by the transducer, and manufacturing one or more transducers for use in the system.

A method of designing a microwave filter using a computerized filter optimizer, comprises generating a filter circuit design in process (DIP) comprising a plurality of circuit elements having a plurality of resonant elements and one or more non-resonant elements, optimizing the DIP by inputting the DIP into the computerized filter optimizer, determining that one of the plurality of circuit elements in the DIP is insignificant, removing the one insignificant circuit element from the DIP, deriving a final filter circuit design from the DIP, and manufacturing the microwave filter based on the final filter circuit design.

A system, methodology, and programming logic for active stormwater controls to optimize sizing and design of Hydromodification Management (HM) structural Best Management Practices (BMPs) to achieve optimal flow duration control. Control logic enables the controlled release of stormwater from a BMP in a manner most akin to pre-development flow duration curves. Inputs to this logic include: flow duration curves based on continuous hydrologic simulation for pre- and post-development conditions; real-time measurement of water level within the BMP; and real-time measurement of discharge entering the BMP. This control logic can interact with control logic for other stormwater management objectives, such as harvest and reuse, infiltration, and combined sewer overflow prevention, and respective inputs, such as real-time weather forecast data, precipitation gage data, downstream flow gauge data, and water quality data, to meet those design objectives as well. New HM BMPs can be optimized to be smaller and, thus, more feasible to implement. Existing stormwater facilities designed for flood control or other management objectives can be retrofitted to provide hydromodification control as well. When utilized with real-time flow and water level monitoring equipment and data, the flow release logic can be adaptively adjusted without physical retrofit of the BMP's outlet.

Obtaining physical model data for CAD model generation with a process that includes: receiving a first acceleration-based path data set including acceleration data for an accelerometer device as it was traced over a first path along the surface of a physical object, converting the first acceleration-based path data set to a first position-based data set including position data for the accelerometer as it was traced over the first path along the surface of the physical object, and generating a three dimensional object model data set based, at least in part on the position data of the first position-based data set.

A method of forming conductive lines in a circuit is disclosed. The method includes arranging a plurality of signal traces in a first set of signal traces and a second set of signal traces, fabricating, using a first mask, a first conductive line for a first signal trace of the first set of signal traces and fabricating, using a second mask, a second conductive line for a second signal trace of the second set of signal traces. Each signal trace of the first set of signal traces has a first width. Each signal trace of the second set of signal traces has a second width different from the first width. The arranging is based on at least a length of a signal trace of the plurality of signal traces.

A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning process by a layout design system. The method also includes allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the self-align double patterning process.

A method for improving OpenCL hardware execution efficiency described in this invention comprises the following steps: compiling a kernel implemented in OpenCL, generating Verilog code with a high-level synthesis tool; analyzing the interfaces of auto-generated Verilog code, recording signals, timing sequence, and function of the interfaces; manually modifying and optimizing the Verilog code; inserting a file replacement command in the script responsible for flow control, replacing the auto-generated code with the optimized Verilog code; rerunning OpenCL compiler and generating an ultimate FPGA configuration file. The invention makes manual optimization of the auto-generated Verilog code becomes possible, by parsing the compilation flow of OpenCL environment and analyzing the structure and interfaces of the auto-generated Verilog code. It promotes the performance of kernels, by increasing working frequency, achieving more parallelism and taking full advantages of FPGA hardware resources, and improves the execution efficiency of OpenCL on FPGA platform significantly.