A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.

A high voltage device includes a substrate, a first LDMOS transistor and a second LDMOS transistor disposed on the substrate. The first LDMOS transistor includes a first gate electrode disposed on the substrate. A first STI is embedded in the substrate and disposed at an edge of the first gate electrode and two first doping regions respectively disposed at one side of the first STI and one side of the first gate electrode. The second LDMOS transistor includes a second gate electrode disposed on the substrate. A second STI is embedded in the substrate and disposed at an edge of the second gate electrode. Two second doping regions are respectively disposed at one side of the second STI and one side of the second gate electrode, wherein the second STI is deeper than the first STI.

Integrated circuit structures including a pillar resistor disposed over a surface of a substrate, and fabrication techniques to form such a resistor in conjunction with fabrication of a transistor over the substrate. Following embodiments herein, a small resistor footprint may be achieved by orienting the resistive length orthogonally to the substrate surface. In embodiments, the vertical resistor pillar is disposed over a first end of a conductive trace, a first resistor contact is further disposed on the pillar, and a second resistor contact is disposed over a second end of a conductive trace to render the resistor footprint substantially independent of the resistance value. Formation of a resistor pillar may be integrated with a replacement gate transistor process by concurrently forming the resistor pillar and sacrificial gate out of a same material, such as polysilicon. Pillar resistor contacts may also be concurrently formed with one or more transistor contacts.

The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.

A semiconductor device for enabling a core device to operate in a safe operating area is provided. The semiconductor devices comprises a core transistor of the core device having a drain configured to receive a first voltage; a dummy device connected to the drain of the core transistor. The dummy device having a first dummy transistor and a second dummy transistor, wherein a gate and a source of the first dummy transistor are connected to each other; a drain of the first dummy transistor is connected to a source of the second dummy transistor, and a gate of the second dummy transistor is connected to the gate of the core transistor.

A display apparatus with a novel structure or a display system with a novel structure is provided. The display system includes a first display apparatus capable of AR display and a second display apparatus. The first display apparatus includes a first display portion displaying a first image superimposed on a transmission image. The second display apparatus includes a second display portion. The first display apparatus has a function of obtaining positional information of the second display portion. A display position of the first image is determined on the basis of the positional information of the second display portion.

A substrate processing device. The device comprises: a first source supply unit; a second source supply unit; a first supply line for connecting the first source supply unit to a spraying unit; a second supply line for connecting the second source supply unit to the spraying unit; a mixing unit provided at the first supply line to be arranged between the first source supply unit and the spraying unit; a first connection line for connecting the second supply line to the first supply line and/or the mixing unit; and a first path change unit provided at a first connection point at which the first connection line is connected to the second supply line, wherein the first path change unit changes the flow path of a second source gas supplied from the second source supply unit.

A method of manufacturing a semiconductor device, including preparing a semiconductor substrate having a main surface, forming a device element structure on the main surface, forming a protective film on the main surface of the semiconductor substrate to protect the device element structure, the protective film having an opening therein, forming at least one material film in a predetermined pattern on the main surface of the semiconductor substrate and in the opening of the protective film, the at least one material film being separate from the protective film by a distance of less than 1 mm, forming a resist film on the main surface of the semiconductor substrate, covering the protective film and the at least one material film, the resist film having an opening therein corresponding to an inducing region for impurity defects, and inducing the impurity defects in the semiconductor substrate, using the resist film as a mask.

A semiconductor device (300A) includes a first layer (20) and a second layer (30) over the first layer. The first layer includes a logic circuit portion (23). The second layer includes a level shifter portion (24) and a pixel circuit (51). The logic circuit portion has a function of supplying a first signal for operating the level shifter portion to the level shifter portion. The level shifter portion has a function of supplying a second signal with a larger amplitude than the first signal to the pixel circuit. The logic circuit portion includes a transistor including silicon in a semiconductor layer where a channel is formed. Each of the level shifter portion and the pixel circuit includes a transistor including a metal oxide in a semiconductor layer where a channel is formed.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor and a capacitor; the transistor includes an oxide, a first conductor and a second conductor over the oxide, a first insulator that is placed over the first conductor and the second conductor and includes a first opening and a second opening, a second insulator in the first opening of the first insulator, and a third conductor over the second insulator; the first opening in the first insulator includes a region overlapping with the oxide; the third conductor includes a region overlapping with the oxide with the second insulator therebetween; the capacitor includes the second conductor, a third insulator in the second opening of the first insulator, and a fourth conductor over the third insulator; and the distance between the first conductor and the second conductor is smaller than the width of the first opening in a cross-sectional view of the transistor in a channel length direction.