A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.

A method of fabricating a memory device is described. Generally, the method includes forming a channel from a semiconducting material overlying a surface of a substrate, and forming dielectric stack on the channel. A first cap layer is formed over the dielectric stack, and a second cap layer including a nitride formed over the first cap layer. The first and second cap layers and the dielectric stack are then patterned to form a gate stack of a device. The second cap layer is removed and an oxidation process performed to form a blocking oxide over the dielectric stack, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate and a body. A compensation network including a gate-coupling circuit couples the gates of each pair of neighboring FETs. The compensation network may further including a body-coupling circuit that couples the bodies of each pair of neighboring FETs.

A power integrated circuit includes a double-diffused metal-oxide-semiconductor (LDMOS) transistor formed in a first portion of the semiconductor layer with a channel being formed in a first body region. The power integrated circuit includes a first deep diffusion region formed in the first deep well under the first body region and in electrical contact with the first body region and a second deep diffusion region formed in the first deep well under the drain drift region and in electrical contact with the first body region. The first deep diffusion region and the second deep diffusion region together form a reduced surface field (RESURF) structure in the LDMOS transistor.

A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.

A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.

The safety is ensured in such a manner that an abnormality of a secondary battery is detected, for example, a phenomenon that lowers the safety of the secondary battery is detected early and a warning is given to a user. A first protection circuit and a second protection circuit are provided for one secondary battery. The first protection circuit includes a memory circuit including a transistor including an oxide semiconductor. Combination of a plurality of protection circuits enables a complementary double protection system in charging, and the safety can be further enhanced.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, and a memory cell including a transistor and a capacitor. The transistor includes an oxide over the first insulator, a first conductor and a second conductor over the oxide, a third insulator over the oxide, and a third conductor over the third insulator. The third insulator and the third conductor are located in a first opening of the second insulator. The capacitor includes a fourth conductor in contact with a top surface of the second conductor, a fourth insulator over the fourth conductor, and a fifth conductor over the fourth insulator. The fourth conductor, the fourth insulator, and the fifth conductor are located in a second opening of the second insulator. A third opening is formed in the first insulator, the second insulator, and the first conductor. A sixth conductor is located in the third opening. The sixth conductor includes a region in contact with part of a top surface of the first conductor and part of a side surface of the first conductor in each of a plurality of layers.

A display apparatus with low power consumption is provided. The display apparatus includes a circuit for boosting a signal voltage output from a gate driver. The signal voltage from the gate driver can be boosted and then supplied to a pixel, which is suitable for driving a display device with a high threshold voltage. Furthermore, by utilizing a boosting function, output of the gate driver can be reduced, and power consumption can also be reduced. By combination with a pixel having a boosting function of image data, a display apparatus with lower power consumption can be achieved.

Provided is a display system with high display quality and high resolution. The display system includes a first layer and a display portion. The display portion is positioned in a region overlapping with the first layer. The first layer includes a semiconductor substrate containing silicon as a material, and a plurality of first transistors and a plurality of second transistors whose channel formation regions contain silicon are formed over the semiconductor substrate. The first layer includes a first circuit and a second circuit; the first circuit includes a driver circuit for driving the display portion; and the second circuit includes a memory device, a GPU, and an EL correction circuit. The display portion includes a pixel, and the pixel includes a light-emitting device containing organic EL and is electrically connected to the driver circuit. The memory device has a function of retaining image data; the GPU has a function of decoding the image data read from the memory device; and the EL correction circuit has a function of correcting light emitted from the light-emitting device.