Patent classifications
H04L12/933
Switch device and recording medium recording failure detection program
A switch device includes: a memory; and a processor coupled to the memory and configured to: identify an adjacent switch device using a function that is operable even when a function of relaying communication is inoperable; confirm communication with the adjacent switch device which is identified, by using the function of relaying communication; and determine whether or not there is a silent failure in the switch device, based on a result of the communication confirmation.
Communication network hopping architecture
Communication network systems are disclosed. In one or more implementations, the communication network system includes a plurality of network devices. Each of the plurality of network devices incorporates one or more multi-port switches, where each multi-port switch includes a connection to the network device incorporating the multi-port switch and a connection to at least one other port of another multi-port switch incorporated by another respective one of the plurality of network devices.
Switch, switch controlling method, and program
A switch has a determining section and a memory managing section. The determining section determines whether or not the node is in a non-ordinary state in which received packets cannot be successfully processed, on a basis of a determination whether or not congestion notification packets received from a node have been continuously received during at least a given period and a determination whether or not a quantity of memory used in a buffer memory which accumulates received packets is at least a given value. The memory managing section deletes, in a case where the node is determined to be in the non-ordinary state, data addressed to the node in the non-ordinary state among data accumulated in the buffer memory.
MULTI-CHIP SYSTEM AND DATA TRANSMISSION METHOD THEREOF
A multi-chip system and a data transmission method thereof are provided. The multi-chip system includes a first chip, a link unit, and a second chip. The first chip includes multiple transmitter (TX) channels and a first data processing module. The TX channels are configured to provide at least one transaction information. The first data processing module converts the at least one transaction information into at least one first data packet according to a general packet format and packs the at least one first data packet according to a specific packet format to generate a second data packet. The first data processing module merges two sets of second data packets into a third data packet and transmits the third data packet to the link unit. The second chip receives the third data packet through the link unit.
SYSTEM AND METHOD FOR PERFORMING TRANSACTION AGGREGATION IN A NETWORK-ON-CHIP (NoC)
System and methods are disclosed for aggregating identical requests sent to a target from multiple initiators through a network-on-chip (NoC). The requests are marked for aggregation. The NoC uses request aggregators (RA) as an aggregation point to aggregate the identical requests that are marked for aggregation. At the aggregation point, the identical requests are reduced to a single request. The single request is sent to the target. The process is repeated in a cascaded fashion through the NoC, possibly involving multiple request aggregators. When a response transaction is received back from the target, which is at the aggregation point closest to the target, the response transaction is duplicated and sent to every original requester, either directly or through other request aggregators, which further duplicate the already duplicated response transaction.
Self identifying interconnect topology
A system for automatically discovering fabric topology includes at least one or more processing units, one or more memory devices, a security processor, and a communication fabric with an unknown topology coupled to the processing unit(s), memory device(s), and security processor. The security processor queries each component of the fabric to retrieve various attributes associated with the component. The security processor utilizes the retrieved attributes to create a network graph of the topology of the components within the fabric. The security processor generates routing tables from the network graph and programs the routing tables into the fabric components. Then, the fabric components utilize the routing tables to determine how to route incoming packets.
Switch with side ports
Data center switches are described. A rack of a data center can include several switches to implement a network topology. The switches can include ports on their fronts and sides such that cables can be coupled with these side ports to implement the network topology.
Network-on-chip topology generation
The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. The HGC is modified based on bridge data and the traffic data to generate a modified HCG. A plurality of traffic graphs (TGs) are constructed based on the physical data, the bridge data, the traffic data and the modified HCG. A candidate topology is generated for each TG, which includes the bridge ports, routers and connections. The candidate topologies are merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.
MULTICAST NETWORK AND MEMORY TRANSFER OPTIMIZATIONS FOR NEURAL NETWORK HARDWARE ACCELERATION
In one embodiment, a system to deterministically transfer partitions of contiguous computer readable data in constant time includes a computer readable memory and a modulo address generator. The computer readable memory is organized into D banks, to contain contiguous data including a plurality of data elements of size M which are constituent data elements of a vector with N data elements, the data elements to start at an offset address O. The modulo address generator is to generate the addresses of the data elements of a vector with i data elements stored in the computer readable memory, the modulo address generator including at least one forward permutaton to permute data elements with addresses of the form O+M*i where 0<=i<N. Other embodiments are described and claimed
System, Apparatus And Method For Adaptive Peer-To-Peer Communication With Edge Platform
In one embodiment, a method includes: receiving, in an edge platform, a plurality of messages from a plurality of edge devices coupled to the edge platform, the plurality of messages comprising metadata including priority information and granularity information; extracting at least the priority information from the plurality of messages; storing the plurality of messages in entries of a pending request queue according to the priority information; selecting a first message stored in the pending request queue for delivery to a destination circuit; and sending a message header for the first message to the destination circuit via at least one interface circuit, the message header including the priority information, and thereafter sending a plurality of packets including payload information of the first message to the destination circuit via the at least one interface circuit. Other embodiments are described and claimed.