H04L12/933

Image processor and methods for processing an image

There may be provided a non-uniform Benes network, that may include a first Benes network portion that has a first number (k) of first inputs and k first outputs; a second Benes network portion that has a second number (j) of second inputs and j second outputs; wherein j is smaller than k; and a set of multiplexers that are coupled between a set of switches of an intermediate layer of the first Benes network portion and a first layer of the second Benes network layer.

Multisite interconnect and policy with switching fabrics

Embodiments herein describe using translation mappings and security contracts to establish interconnects and policies between switching fabrics at different sites to create a unified fabric. In one embodiment, a multi-site controller can stretch endpoint groups (EPGs) between the sites so that a host or application in a first site can communicate with a host or application in a second site which is assigned to the same stretched EPG, despite the two sites have different namespaces. Further, the shadow EPGs can be formed to facilitate security contracts between EPGs in different sites. Each site can store namespace translation mapping that enable the site to convert namespace information in packets received from a different site into its own namespace values. As a result, independent bridging and routing segments in the various sites can be interconnected as well as providing application accessibility across different fabrics with independent and private namespaces.

Cooling system for a networking device with orthogonal switch bars

A cooling system for a networking device may be provided. The networking device may comprise a first plurality of switch bars each comprising a first switch type arranged parallel to one another, a second plurality of switch bars each comprising a second switch type arranged parallel to one another, and a third plurality of switch bars each comprising a third switch type arranged parallel to one another. The first plurality of switch bars, the second plurality of switch bars, and the third plurality of switch bars may be arranged orthogonally. A plurality of cooling passages may be configured to supply a coolant to the apparatus and to exhaust the coolant from the apparatus. The coolant may pass through the first plurality of switch bars, the second plurality of switch bars, and the third plurality of switch bars.

DATA TRANSMISSION SYSTEM
20210352025 · 2021-11-11 · ·

The present invention relates to a data transmission system comprising a data exchange unit; wherein, to transmit a data frame, it passes successively at least through an interface module that is configured to receive said data frame from outside the transmission system; an analysis and filtering module responsible for processing said data frame which is received from the interface module before encapsulation; and an encapsulation module responsible for encapsulating said data frame processed by the analysis and filtering module, wherein two successive modules through which said data frame passes are connected to one another by an interconnection device each comprising a temporary memory for storing said frame and the read and write accesses to said memory being frequency-independent.

System and method for supporting SMA level abstractions at router ports for inter-subnet exchange of management information in a high performance computing environment

Systems and methods for supporting SMA level abstractions at router ports for inter-subnet exchange of management information in a high performance computing environment. In accordance with an embodiment, a subnet manager in a local subnet is responsible for establishing and configuring a remote attribute a switch having a switch port configured as a router port. This remote attribute can comprise certain information about the local subnet, including connectivity information and port status information. On receiving a query from a remote subnet manager, via a SMP (or a vendor specific SMP), information contained in the remote attribute can be communicated back to the remote subnet manager.

Non-blocking switch matrix
11171886 · 2021-11-09 · ·

A N×M non-blocking switch matrix, where N and M are integers, includes an input stage having a plurality of m/2-way multiport switches, where quotient m/2 is a positive integer less than M, and an output stage having a plurality of n/2-way multiport switches, where quotient n/2 is a positive integer less than N. The switch matrix further includes a transfer stage having a plurality of transfer switches operatively connected between the input stage and output stage, and selectively applying outputs of the m/2-way multiport switches to inputs of the n/2-way multiport switches such that any given input to the m/2-way multiport switches is connectable to any given output of the n/2-way multiport switches.

Flexible Clos topology switch
11171882 · 2021-11-09 · ·

In one embodiment, a computer network system, includes at least one lower tier of lower switches, at least one upper tier of upper switches, and a middle tier of middle switches connected down-tier to ones of the lower switches and up-tier to ones of the upper switches, one of the middle switches including a clos topology arrangement of leaf and spine switches, the leaf switches being connected via K internal network connections to the spine switches, each leaf switch being connected to each spine switch, the leaf switches being connected via N down-tier network connections to ones of the lower switches and via M up-tier network connections to ones of the upper switches, there being more of the N down-tier network connections than there are of the M up-tier network connections, and there being less of the K internal network connections than there are of the N and M connections.

Reducing power consumption in an electronic device
11171890 · 2021-11-09 · ·

An ingress packet processor in a device corresponds to a group of ports and receives network packets from ports in its port group. A traffic manager in the device manages buffers storing packet data for transmission to egress packet processors. An ingress arbiter is associated with a port group and connects the port group to an ingress packet processor coupled to the ingress arbiter. The ingress arbiter determines a traffic rate at which the associated ingress packet processor transmits packets to the traffic manager. The ingress arbiter controls an associated traffic shaper to generate a number of tokens that are assigned to the port group. Upon receiving packet data from a port in the group, the ingress arbiter determines, using information from the traffic shaper, whether a token is available. Conditioned on determining that a token is available, the ingress arbiter forwards the packet data to the ingress packet processor.

Automatic Network Assembly
20210344563 · 2021-11-04 ·

Some examples provide a method for automatic network assembly. The following instructions may be used to implement automatic network assembly in a modular infrastructure. Instructions to automatically connect a management port to a management network. Instructions to automatically connect link ports to form a scalable ring. Instructions to automatically connect each modular infrastructure management device to a bay management network port.

METHOD FOR IMPLEMENTING A LINE SPEED INTERCONNECT STRUCTURE
20210342159 · 2021-11-04 · ·

A method and apparatus including a cache controller coupled to a cache memory, wherein the cache controller receives a plurality of cache access requests, performs a pre-sorting of the plurality of cache access requests by a first stage of the cache controller to order the plurality of cache access requests, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of cache access requests in parallel to map the plurality of cache access requests from a first position to a second position corresponding to ports or banks of a cache memory, performs the combining and splitting of the plurality of cache access request by a second stage of the cache controller, and applies the plurality of cache access requests to the cache memory at line speed.