A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

A network comprising interconnected first and second processors, each processor comprising one or more of: multiple processing units arranged on a chip configured to execute program code; an on-chip interconnect comprising groups of exchange paths connected to receive data from corresponding groups of the processing units; external interfaces configured to communicate data off-chip as packets, each having a destination address, external interfaces of the first and second processors being connected by an external link; multiple exchange blocks, each connected to groups of the exchange paths; a routing bus configured to route packets between the exchange blocks and the external interfaces. Processing units of the first processor generate off-chip packets such that the group of processing units serviced by the first exchange block on the first processor address off-chip packets to the group of processing units on the second processor serviced by the corresponding first exchange block of the second processor.

Systems and methods are disclosed for reducing latency and power consumption of on-chip movement through an approximate communication framework for network-on-chips (“NoCs”). The technology leverages the fact that big data applications (e.g., recognition, mining, and synthesis) can tolerate modest error and transfers data with the necessary accuracy, thereby improving the energy-efficiency and performance of multi-core processors.

An interconnection network for a processing unit having an array of cores. The interconnection network includes routers and adaptable links that selectively connect routers in the interconnection network. For example, each router may be electrically connected to one or more of the adaptable links via one or more multiplexers and a link controller may control the multiplexers to selectively connect routers via the adaptable links. In another example, adaptable links may be formed as part of an interposer and the link controller selectively connect routers via the adaptable links in the interposer using interposer switches. The adaptable links enable the interconnection network to be dynamically partitioned. Each of those partitions may be dynamically reconfigured to form a topology.

Embodiments disclosed herein generally relate to the use of Network-on-Chip architecture for solid state memory structures, both volatile and non-volatile, which provide for the access of memory storage blocks via a router. As such, data may be sent to and/or from the memory storage blocks as data packets on the chip. The Network-on-Chip architecture may further be utilized to interconnect unlimited numbers of memory cell matrices, spread on a die, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits may include improved signal integrity, larger die areas available to implement memory arrays, and higher frequency of operation.

In one embodiment, a method is performed at a controller of a fabric that is connected to a first seed device in the fabric. The method includes obtaining a connectivity graph of the fabric including the first seed device. The method further includes causing the first seed device to send a first request to a first neighboring device in the connectivity graph via a first interface of the first seed device connectable to the first neighboring device. The method also includes assigning fabric component properties to devices in the fabric based at least in part on a first message from the first seed device, where the first seed device generates the first message based at least in part on a first response from the first neighboring device received via the first interface. The method additionally includes converting the first neighboring device to a second seed device in the fabric.

A multi-fabric VLAN configuration system includes a first fabric with server devices that are configured to communicate using VLANs, a primary I/O module coupled to the server devices, and a first fabric management system coupled to the server devices and the primary I/O module. The first fabric management system identifies VLAN information associated with the VLANs, automatically configures the primary I/O module using the VLAN information, and causes the VLAN information to be transmitted by the primary I/O module. A second fabric in the multi-fabric VLAN configuration system includes a leaf switch device that is coupled to the primary I/O module and that receives the VLAN information, and a second fabric management system that is coupled to the leaf switch device and that receives the VLAN information from the leaf switch device, and automatically configures the leaf switch device using the VLAN information.

System and method for supporting scalable representation of switch port status in a high performance computing environment. In accordance with an embodiment, a scalable representation of switch port status can be provided. By adding a scalable representation of switch port status at each switch (both physical and virtual)—instead of getting all switch port changes individually, the scalable representation of switch port status can combine a number of ports that can scale by just using a few bits of information for each port's status.

Provided is a digital switch including: a plurality of input-side memories, which are arranged in a one-to-one correspondence with a plurality of input ports, and are configured to accumulate time-division multiplexed data; a plurality of output-side memories, which are arranged in a one-to-one correspondence with a plurality of output ports, and are configured to accumulate time-division multiplexed data; and a switch matrix configured to receive, as input, the time-division multiplexed data read out in every cycle from each of the plurality of input-side memories, and execute routing for selecting, in accordance with a connection control signal received from outside, any one of the plurality of output-side memories such that the time-division multiplexed data read out in every cycle is output from each of the plurality of output ports without causing a difference in delay, to output the time-division multiplexed data.

A system for hot swapping a network switch without disconnecting the network switch connectors is provided. The system disaggregates the switch faceplate network cable connectors from the internal components of the network switch so that the internal switch components may be removed from the switch without disconnecting the switch network cables.