Patent classifications
H04L12/933
System for providing access to the internet
A system for providing access to the internet, comprises a network of routers (R) hereinafter designated “new routers”) wherein each new router (R) has a CPU (112) that has, or is associated with, a public area (142) that allows simultaneous access to the new router's CPU by more than one user account. The system is so arranged that a pre-registered user with a user account identified by an identifier, typically a user name and/or password, can access the internet from any new router (R) in the network by connecting to the public area (142) of the new router's CPU (112) and entering the account identifier of the pre-registered user account.
Command injection to hardware pipeline for atomic configuration
A command processing system facilitates pipeline configuration. Each stage of a packet processing pipeline may access certain memory locations for processing of a data packet as it passes through each stage. The command processing system facilitates changing the memory locations in an atomic manner.
Method and A First Device for Managing Data Frames in Switched Networks
A method and a first device (110) of a switched network (100), for managing data frames received, at a first port, from a second device (120) are disclosed. The first device (110) handles the first port and a second port for transfer of data frames between the first and second devices (110, 120). The first device (110) is addressable by a Media Access Control address, “MAC address”, associated with the first port. The first device (110) receives (201), from the second device (120), at least one data frame at the second port. The first device (110) sends (202), on the first port, a message including the MAC address associated with the first port.
GENERATING PHYSICALLY AWARE NETWORK-ON-CHIP DESIGN FROM A PHYSICAL SYSTEM-ON-CHIP SPECIFICATION
Different example implementations of the present disclosure relates to methods and computer readable mediums for automatically generating physically aware NoC design and physically aware NoC Specification based on one or more of given SoC architectural details, physical information of SoC, traffic specification, power profile and one or more constraints. The method includes steps of receiving input information, determining the location/position of different NoC agents, interconnecting channels, pins, I/O interfaces, physical/virtual boundaries, number of layers, size/depth/width of different channels at different time, and locating/configuring the different NoC agents, interconnecting channels, pins, I/O interfaces, and physical/virtual boundaries.
Dynamic adjustment of quality of service parameters
A computer-implemented method for dynamic adjustment of quality of service parameters is described. In one embodiment, one or more quality of service (QoS) parameters of a client of a mesh network is set based on an expected bandwidth for the mesh network. An actual bandwidth for the mesh network is measured. One or more QoS parameters of the client is automatically changed in response to the actual bandwidth differing from the expected bandwidth. The change in the QoS parameters may be configured to compensate for the difference between the actual bandwidth and the expected bandwidth.
Address learning and aging for network bridging in a network processor
Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination address is stored in an address table stored in a shared memory of the network processor. The I/O adapter memory has lower access latency than the address table. If the destination address is stored in the address table, the received data packet is processed in accordance with bridging rules stored in the address table and the bridging rules stored in the I/O adapter memory are updated.
Methods and apparatus for enabling communication between network elements that operate at different bit rates
A method for enabling network elements (NEs) operating at a bit rate R.sub.1 to communicate with NEs operating at a bit rate R.sub.2 is described. A ratio of R.sub.2 to R.sub.1 is represented by a ratio M:N, M and N are positive integers, and M>N. The method includes providing a number M×K of the NEs operating at a bit rate R.sub.1, each of the M×K NEs including a communication interface communicating at the bit rate R.sub.1, where K is a positive integer, providing a number N×K of transceivers operating at the bit rate R.sub.2, each of the N×K transceivers including an M:N electrical interface which enables translation between bit rates whose ratio is represented by the ratio M:N, bypassing the communication interfaces of the M×K NEs by interconnecting electrical lanes of the M×K NEs with the M:N electrical interfaces of the N×K transceivers, and using at least one of the N×K transceivers for communicating data between at least one of the M×K NEs interconnected with the at least one of the N×K transceivers and at least one of the NEs operating at the bit rate R.sub.2. Related apparatus and methods are also described.
MAC address synchronization in a fabric switch
One embodiment of the present invention provides a system for facilitating synchronization of MAC addresses in a fabric switch. During operation, the system divides a number of media access control (MAC) addresses associated with devices coupled to an interface of the switch. The system then computes a checksum for a respective chunk of MAC addresses. In addition, the system broadcasts MAC address information of the chunk to facilitate MAC address synchronization in a fabric switch of which the switch is a member, and to manage the chunks and their corresponding checksum, thereby correcting an unsynchronized or race condition in the fabric switch.
Industrial control device and method for insertion and removal of a module under power without interruption
Disclosed is an industrial control device including a point-to-point backplane/point module architecture providing RIUP (Removal and Insertion Under Power) functionality where data communications between modules is maintained after the removal of a point module from the backplane. According to an exemplary embodiment, a backplane includes a plurality of bypass switches controlled by respective point modules, whereby data communicated bypass a removed point module interface and point-to-point data communications are provided to an inserted point module after an initial routine is executed by a microcontroller associated with the inserted point module.
Network device and a method for networking
A networking device including a plurality of client ports arranged for communicating with a plurality of clients, a service port arranged for communicating with a machine arranged to communicate with the plurality of clients, and networking componentry arranged to communicate electromagnetic communications between the plurality of client ports and the service port.