Patent classifications
H01L43/06
MAGNETIC ELEMENT AND MAGNETIC MEMORY ARRAY
A magnetic element according to an embodiment includes a wiring layer extending in a first direction and including a ferromagnetic material and a nonmagnetic layer laminated on the wiring layer in a second direction. The wiring layer includes a side surface inclined with respect to the second direction in a cross section orthogonal to the first direction. The side surface has one or more bending points at which an inclination angle with respect to the second direction becomes discontinuous. An inclination angle of a first inclined surface far from the nonmagnetic layer is smaller than an inclination angle of a second inclined surface close to the nonmagnetic layer in a state in which a first bending point at a position farthest from the nonmagnetic layer among the bending points is interposed between the inclination angles.
Bismuth antimony alloys for use as topological insulators
A SOT device includes a bismuth antimony dopant element (BiSbE) alloy layer over a substrate. The BiSbE alloy layer is used as a topological insulator. The BiSbE alloy layer includes bismuth, antimony, AND a dopant element. The dopant element is a non-metallic dopant element, a metallic dopant element, and combinations thereof. Examples of metallic dopant elements include Ni, Co, Fe, CoFe, NiFe, NiCo, NiCu, CoCu, NiAg, CuAg, Cu, Al, Zn, Ag, Ga, In, or combinations thereof. Examples of non-metallic dopant elements include Si, P, Ge, or combinations thereof. The BiSbE alloy layer can include a plurality of BiSb lamellae layers and one or more dopant element lamellae layers. The BiSbE alloy layer has a (012) orientation.
Isolated hall sensor structure
An isolating Hall sensor structure having a support structure made of a substrate layer and an oxide layer, a semiconductor region of a first conductivity type which is integrally connected to a top side of the oxide layer, at least one trench extending from the top side of the semiconductor region to the oxide layer of the support structure, at least three first semiconductor contact regions of the first conductivity type, each extending from a top side of the semiconductor region into the semiconductor region. The at least one trench surrounds a box region of the semiconductor region. The first semiconductor contact regions are each arranged in the box region of the semiconductor region and are each spaced apart from one another. A metallic connection contact layer is arranged on each first semiconductor contact region.
Integrated rotation-angle sensor unit in a measuring system for rotation angle determination
An integrated rotation-angle sensor unit in a measuring system for rotation angle determination, with a shaft that is rotatable about an axis of rotation with a transmitter, The sensor unit has a semiconductor layer with a top surface that can be arranged perpendicular to the axis of rotation and has a bottom surface, and two monolithic Hall sensor systems are implemented in the semiconductor layer. Each Hall sensor system has at least a first Hall sensor, a second Hall sensor, and a third Hall sensor, and the three Hall sensors of the first Hall sensor system are arranged on a first circle that is parallel to the top surface of the semiconductor layer and can be arranged concentrically around the axis of rotation.
BiSb topological insulator with seed layer or interlayer to prevent sb diffusion and promote BiSb (012) orientation
A spin-orbit torque (SOT) magnetic tunnel junction (MTJ) device includes a substrate, a seed layer over the substrate, and a bismuth antimony (BiSb) layer having (0120) orientation on the seed layer. The seed layer includes a silicide layer and a surface control layer. The silicide layer includes a material of NiSi, NiFeSi, NiFeTaSi, NiCuSi, CoSi, CoFeSi, CoFeTaSi, CoCuSi, or combinations thereof. The surface control layer includes a material of NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoM, CoNiM, CoNi, NiSi, CoSi, NiCoSi, Cu, CuAgM, CuM, or combinations thereof, in which M is Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si.
STORAGE UNIT AND DATA WRITING AND READING METHODS THEREOF, MEMORY AND ELECTRONIC DEVICE
The present disclosure provides a storage unit, a data writing method and a data reading method thereof, a memory and an electronic device. The storage unit includes a semiconductor substrate, a first insulating medium layer, a ferroelectric thin film layer, a bottom electrode, a tunnel junction, a first metal interconnection portion, a second metal interconnection portion, a third metal interconnection portion and a fourth metal interconnection portion. The first insulating medium layer is formed on the semiconductor substrate, the ferroelectric thin film layer is disposed on the first insulating medium layer, the bottom electrode is formed on the ferroelectric thin film layer, and the tunnel junction is formed on the bottom electrode. The first metal interconnection portion is connected to a first end of the bottom electrode, and the third metal interconnection portion is connected to a second end of the bottom electrode. The second metal interconnection portion is connected to the ferroelectric thin film layer, and the fourth metal interconnection portion is connected to the tunnel junction. As compared with the prior art, the present disclosure can control a directional flipping of the magnetic moment in the tunnel junction based on the ferroelectric thin film layer provided. Based on the structural design of the storage unit, the present disclosure does not require an external magnetic field, and fully meets the requirement of high integration of the device.
SEMICONDUCTOR DEVICE WITH CMOS PROCESS BASED HALL SENSOR AND MANUFACTURING METHOD
A semiconductor device including a CMOS process-based Hall sensor is provided. The semiconductor device which may include a N-type sensing region which is formed on a semiconductor substrate; P-type contact regions and N-type contact regions which are alternately formed in the N-type sensing region; a plurality of first trenches which are formed in contact with the P-type contact regions and have a first width; and a plurality of second trenches which separate the P-type contact regions and the N-type contact regions and have a second width less than the first width.
Semiconductor device
A semiconductor device includes a semiconductor substrate: a vertical Hall element formed in the semiconductor substrate, and having a magnetosensitive portion; a first excitation wiring disposed above the magnetosensitive portion, and configured to apply a first calibration magnetic field (M1) to the magnetosensitive portion; and second excitation wirings disposed above the magnetosensitive portion on one side and on another side of the first excitation wiring, respectively, along the first excitation wiring as viewed in plan view from immediately above a front surface of the semiconductor substrate, and configured to apply second calibration magnetic fields (M2) to the magnetosensitive portion.
Multi-contact hall plate having contacts equally distributed along an inner edge region of the hall plate
A multi-contact Hall plate having four contacts or a multiple of four contacts, wherein each of the contacts is arranged substantially equally distributed along an edge region of the Hall plate, and each of the contacts is connected to one of the four terminals.
Manufacturing method for multilayer structure of magnetic body and BiSb layer, magnetoresistive memory, and pure spin injection source
A magnetoresistive memory cell includes an MTJ element including a magnetization free layer and a pure spin injection source. The pure spin injection source includes a BiSb layer coupled to the magnetization free layer. By flowing an in-plane current through the BiSb layer, this arrangement is capable of providing magnetization reversal of the magnetization free layer.