A network-traversal method includes: receiving an address information of a network device from a link server; generating a port number sequence composed of port values according to an external port number of the address information; and sending a link packet to an external network address of the address information in an order of the port values in the port number sequence until receiving an acknowledgement packet from the network device. At least one of the port values is related to the external port number. A part of the rest port values is/are generated gradually based on the external port number, and the others of the rest port values is/are generated randomly.

A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

A method and system for configuring communications over a physical communication link connected between a physical port of a network switch and a physical port of a physical network interface on an end station. The communication link between the physical port of the network switch and the physical port of the physical network interface is logically partitioned into a number of channels of communication. For each channel, a channel profile is generated that defines properties of that channel. The physical network interface is instructed to self-configure such that the physical network interface is able to communicate with the network switch over each channel in accordance with the channel profile defined for that channel.

Systems, methods and apparatus regarding network configuration and network switches including an in-line Network Console Access (NETCONA) Device having a NETCONA Management Module, a NETCONA WAN-side Port, a NETCONA LAN-side Port, and at least one NETCONA Serial Console Access Port. The NETCONA Device may share a single IP address for “out-of-band” access to network appliances at a network edge point. The NETCONA Device uses packet forwarding to transparently transfer data between a WAN and a LAN. Data packets having console access information are forwarded to the NETCONA Management Module for processing. An exemplary network system includes an in-line NETCONA Device and at least one Network Appliance; wherein the Network Appliance includes a Network Appliance Serial Console Access Port; and wherein the NETCONA Serial Console Access Port is coupled with the Network Appliance Serial Console Access Port to enable Serial Console Access. Numerous other aspects are provided.

Some embodiments provide a method for implementing a logical router in a network. The method receives a definition of a logical router for implementation on a set of network elements. The method defines several routing components for the logical router. Each of the defined routing components includes a separate set of routes and separate set of logical interfaces. The method implements the several routing components in the network. In some embodiments, the several routing components include one distributed routing component and several centralized routing components.

Continuing to integrate more aggregate bandwidth and higher radix into switch devices is an economic imperative because it creates value both for the supplier and customer in large data center environments which are an increasingly important part of the marketplace. While new silicon processes continue to shrink transistor and other chip feature dimensions, process technology cannot be relied upon as a key driver of power reduction. Transitioning from 28 nm to 16 nm is a special case where FinFET provides additional power scaling, but subsequent FinFET nodes are not expected to deliver as substantial of power reductions to meet the desired increases in integration. The disclosed switch architecture attacks the power consumption problem by controlling the rate at which power-consuming activities occur.

In a core node, packet related information included in a packet is extracted, a virtual queue length, which is an estimated value of a queue length of a transmission queue addressed to a user in an edge device, is calculated and held on a user basis on the basis of the packet related information and band information of a line between the edge device and the user, and a determination is made, on a user basis, as to whether or not band control is required, on the basis of the virtual queue length and predetermined conditions so as to perform, on the basis of the result of the determination, the band control of the packet addressed to the user on a user basis in a packet relay part.

A crossbar switch has N input ports, M output ports, and a switching matrix with N×M crosspoints. In an embodiment, each crosspoint contains an internal queue (XQ), which can store one or more packets to be routed. Traffic rates to be realized between all Input/Output (IO) pairs of the switch are specified in an N×M traffic rate matrix, where each element equals a number of requested cell transmission opportunities between each IO pair within a scheduling frame of F time-slots. An efficient algorithm for scheduling N traffic flows with traffic rates based upon a recursive and fair decomposition of a traffic rate vector with N elements, is proposed. To reduce memory requirements a shared row queue (SRQ) may be embedded in each row of the switching matrix, allowing the size of all the XQs to be reduced. To further reduce memory requirements, a shared column queue may be used in place of the XQs. The proposed buffered crossbar switches with shared row and column queues, in conjunction with the row scheduling algorithm and the DCS column scheduling algorithm, can achieve high throughput with reduced buffer and VLSI area requirements, while providing probabilistic guarantees on rate, delay and jitter for scheduled traffic flows.

A method and system provide an information centric network with a software defined network based on an information centric networking protocol on top of a physical network based on the internet protocol. There are forwarding elements in the physical network and a controller in the software defined network for controlling the forwarding elements. A publicly routable network address per domain for outside data object requests of named data objects is announced via the information centric network, and upon a first packet of an object request being received by an ingress element of the information centric network, the first packet is forwarded to the controller. The controller determines an object source for the requested named data object, encodes a message id into a header of the packet and establishes a forwarding path to forward the packet and further packets to the determined object source.

A switching device includes a processor, an input buffer, an output buffer, and a Banyan switching architecture, where the processor is configured to convert an initial switching table to a non-congestion switching table and an order-adjustment table using a preset reordering algorithm; the input buffer is configured to save first period data that is from an input port; the processor is further configured to perform, using the non-congestion switching table, data switching on data in the first full-period data saved in the input buffer, to obtain second full-period data; the Banyan switching architecture is configured to perform synchronous data switching on the second full-period data; the output buffer is configured to save the second full-period data on which the synchronous data switching has been performed; the processor is further configured to adjust, using the order-adjustment table, a data order of the second period data.