Processing packets in a system that includes a plurality of interconnected processing cores is described. The processing includes receiving packets into one or more queues, associating at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate, mapping a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and at least one rate associated with a node not in the set, and processing the packets in the mapped processor cores according to the hierarchy.

Systems disclosed herein may allocate buffer space using methods, which prevent other resource allocation methods from apportioning the other resources in a way that inhibits system needs from being met. As such, buffer space may be dynamically allocated without impeding other resource allocation by basing the buffer space allocation at least on the traffic priority class that each allocated buffer will handle. Alternatively, buffer space may be dynamically allocated without impeding other resource allocation by basing the buffer space allocation at least on the bandwidth needs of each respective buffer being allocated. Alternatively still, buffer space may be dynamically allocated without impeding other resource allocation by basing the buffer space allocation at least on a function of the traffic priority class that each allocated buffer will handle and the bandwidth needs of each respective buffer being allocated.

Some embodiments provide a method for implementing a logical router in a network. The method receives a definition of a logical router for implementation on a set of network elements. The method defines several routing components for the logical router. Each of the defined routing components includes a separate set of routes and separate set of logical interfaces. The method implements the several routing components in the network. In some embodiments, the several routing components include one distributed routing component and several centralized routing components.

Described are network coding (NC) systems and techniques which utilize multiple composite extension finite fields to reduce complexity at various nodes in a network and also reduce overhead due to signal coding coefficients. A coding design uses a series of finite fields where increasingly larger fields are based on a previous smaller field. Techniques disclosed herein can be applied to existing systems using Random Linear Network Coding (RLNC) or Fulcrum codes.

Continuing to integrate more aggregate bandwidth and higher radix into switch devices is an economic imperative because it creates value both for the supplier and customer in large data center environments which are an increasingly important part of the marketplace. While new silicon processes continue to shrink transistor and other chip feature dimensions, process technology cannot be relied upon as a key driver of power reduction. Transitioning from 28 nm to 16 nm is a special case where FinFET provides additional power scaling, but subsequent FinFET nodes are not expected to deliver as substantial of power reductions to meet the desired increases in integration. The disclosed switch architecture attacks the power consumption problem by controlling the rate at which power-consuming activities occur.

Methods and apparatus for accelerating VM-to-VM Network Traffic using CPU cache. A virtual queue manager (VQM) manages data that is to be kept in VM-VM shared data buffers in CPU cache. The VQM stores a list of VM-VM allow entries identifying data transfers between VMs that may use VM-VM cache “fast-path” forwarding. Packets are sent from VMs to the VQM for forwarding to destination VMs. Indicia in the packets (e.g., in a tag or header) is inspected to determine whether a packet is to be forwarded via a VM-VM cache fast path or be forwarded via a virtual switch. The VQM determines the VM data already in the CPU cache domain while concurrently coordinating with the data to and from the external shared memory, and also ensures data coherency between data kept in cache and that which is kept in shared memory.

A switching device includes a processor, an input buffer, an output buffer, and a Banyan switching architecture, where the processor is configured to convert an initial switching table to a non-congestion switching table and an order-adjustment table using a preset reordering algorithm; the input buffer is configured to save first period data that is from an input port; the processor is further configured to perform, using the non-congestion switching table, data switching on data in the first full-period data saved in the input buffer, to obtain second full-period data; the Banyan switching architecture is configured to perform synchronous data switching on the second full-period data; the output buffer is configured to save the second full-period data on which the synchronous data switching has been performed; the processor is further configured to adjust, using the order-adjustment table, a data order of the second period data.

Embodiments are directed to detecting one or more attacks in a network. One or more network flows may be monitored using one or more network monitoring computers (NMCs). If one or more file write operations are detected based on information included in one or more packets of the one or more network flows, one or more detection rules may be executed to analyze one or more portions of the one or more packets to identify file information that is associated with the one or more file write operations. One or more metrics may be provided based on the one or more detection rules and one or more of the file information, the one or more file write operations, or the like. If one or more metrics exceed one or more threshold values, one or more reports of one or more attacks may be provided.

A system and method for protocol independent receive side scaling (RSS) includes storing a plurality of RSS hash M-tuple definitions, each definition corresponding to one of a set of possible protocol header combinations for routing an incoming packet, the set of possible protocol header combinations being modifiable to include later-developed protocols. Based on initial bytes of the incoming packet, a pattern of protocol headers is detected, and used to select one of the plurality of RSS hash M-tuple definitions. The selected RSS hash M-tuple definition is applied as a protocol-independent arbitrary set of bits to the headers of the incoming packet to form a RSS hash M-tuple vector, which is used to compute a RSS hash. Based on the RSS hash, a particular queue is selected from a set of destination queues identified for the packet, and the packet is delivered to the selected particular queue.

Methods and apparatus for sending packets using optimized PIO write sequences without sfences and out-of-order credit returns. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received by a processor in an original order and executed out of order, resulting in the packet data being written to send blocks in the PIO send memory out of order, while the packets themselves are stored in sequential order once all of the packet data is written. The packets are egressed out of order by egressing packet data contained in the send blocks to an egress block using a non-sequential packet order that is different than the sequential packet order. In conjunction with egressing the packets, corresponding credits are returned in the non-sequential packet order. A block list comprising a linked list and a free list are used to facilitate out-of-order packet egress and corresponding out-of-order credit returns.