An integrated sensor device includes: a semiconductor substrate comprising a horizontal Hall element, and an integrated magnetic flux concentrator located substantially above said horizontal Hall element, wherein the first magnetic flux concentrator has a shape with a geometric center which is aligned with a geometric centre of the horizontal Hall element; and wherein the shape has a height H and a transversal dimension D, wherein H≥30 μm and/or wherein (H/D)≥25%. The integrated magnetic flux concentrator may be partially incorporated in the “interconnection stack”. A method is provided for producing such an integrated sensor device.

Disclosed is a magnetic device including a spin sinker. The magnetic device includes a storage medium, a spin sinker, and a read node. The storage medium receives an in-plane current from outside and generates a self-generated spin current that perpendicularly flows to a charge current, thereby controlling a data structure with the self-generated spin current. The spin sinker receives and attenuates the spin current. The read node measures a magnetoresistance of a data structure through the storage medium. The storage medium is made of a magnetic metal and the spin sinker is made of a magnetic insulating material.

A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.

A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.

A magnetoresistive memory device includes a magnetic tunnel junction including a free layer, at least two tunneling dielectric barrier layers, and at least one metallic quantum well layer. The quantum well layer leads to the resonant electron tunneling through the magnetic tunnel junction in such a way that it strongly enhances the tunneling probability for one of the magnetization states of the free layer, while this tunneling probability remains much smaller in the opposite magnetization state of the free layer. The device can be configured in a spin transfer torque device configuration, a voltage-controlled magnetic anisotropy, a voltage controlled exchange coupling device configuration, or a spin-orbit-torque device configuration.

A spin-orbit torque magnetization rotational element includes: a first insulating layer with first and second openings; a first conductive portion formed inside the first opening; a second conductive portion formed inside the second opening; a spin-orbit torque wiring located in a first direction and extends in a second direction over the first and second conductive portions; and a first ferromagnetic layer located on the side opposite to the first insulating layer in the spin-orbit torque wiring, wherein the first conductive portion includes a first surface facing the spin-orbit torque wiring, a second surface facing the first surface and is located at a position farther from the spin-orbit torque wiring than the first surface, and a side surface connecting the first surface and the second surface, and the side surface includes a continuous major surface and a third surface inclined or curved and is discontinuous with respect to the major surface.

A memory device may comprise a substrate defining a main plane; a plurality of memory cells each comprising a SOT current layer disposed in the main plane of the substrate and a magnetic tunnel junction residing on the SOT current layer; and a bit line and a source line to flow a write current in a write path including the SOT current layer of a selected memory cell. The source line comprises a conductive magnetic material providing a magnetic bias field extending to the magnetic tunnel junction of the selected memory cell for assisting the switching of the cell state when the write current is flowing.

The present disclosure provides a spin-orbit torque structure having a high spin Hall angle and low resistance by including a topological material. In addition, the present disclosure provides a spin-orbit torque structure having a low power consumption density by including a topological material. Also, a magnetic memory device including the spin-orbit torque structure is provided.

Methods for forming an integrated circuit are provided. Aspects include providing a wafer substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure, the memory area interconnect structure comprising metal interconnects formed within a first interlayer dielectric, recessing a portion of the memory area interconnect structure, forming a bottom electrode contact on the recessed portion of the memory area interconnect structure, forming a bottom electrode over the bottom electrode contact, forming a protective dielectric layer over the non-memory area interconnect structure, and forming memory element stack layers on a portion of the bottom electrode.

A spin element includes an element portion including a first ferromagnetic layer, a conducting portion that extends in a first direction as viewed in a lamination direction of the first ferromagnetic layer and faces the first ferromagnetic layer, and a current path extending from the conducting portion to a semiconductor circuit and having a resistance adjusting portion between the conducting portion and the semiconductor circuit, wherein the resistance value of the resistance adjusting portion is higher than the resistance value of the conducting portion, and the temperature coefficient of the volume resistivity of a material forming the resistance adjusting portion is lower than the temperature coefficient of the volume resistivity of a material forming the conducting portion.