An ultra-fast magnetic random access memory (MRAM) comprises a three terminal composite SOT magnetic tunneling junction (CSOT-MTJ) element including a magnetic flux guide (MFG) having a very high magnetic permeability, a spin Hall channel (SHC) having a large positive spin Hall angle, an in-plane magnetic memory (MM) layer, a tunnel barrier (TB) layer, and a magnetic pinning stack (MPS) having a synthetic antiparallel coupling pinned by an antiferromagnetic material. The magnetic writing is significantly boosted by a combined effort of enhanced spin orbit torque (SOT) and Lorentz force generated by current-flowing wire (CFW) in the SHC layer and spin transfer torque (STT) by a current flowing through the MTJ stack, and further enhanced by a magnetic close loop formed at the cross section of MFG/SHC/MM tri-layer.

A magnetoelectric memory device includes a magnetic tunnel junction located between a first electrode and a second electrode. The magnetic tunnel junction includes a reference layer, a nonmagnetic tunnel barrier layer, a free layer, and a dielectric capping layer. At least one layer that provides voltage-controlled magnetic anisotropy is provided within the magnetic tunnel junction, which may include a pair of nonmagnetic metal dust layers located on, or within, the free layer, or a two-dimensional metal compound layer including a compound of a nonmagnetic metallic element and a nonmetallic element.

A semiconductor device including a magnetic tunnel junction stack, a metallic hard mask aligned above the magnetic tunnel junction stack and an air gap surrounding the metallic hard mask. A method including forming a magnetic tunnel junction stack, forming a metallic hard mask aligned above the magnetic tunnel junction stack, conformally forming a dielectric over the metallic hard mask and the magnetic tunnel junction stack, forming barrier on vertical side surfaces of the dielectric, and removing the dielectric between the metallic hard mask and the barrier. A method including forming a magnetic tunnel junction stack, forming a metallic hard mask aligned above the magnetic tunnel junction stack, conformally forming a dielectric over the metallic hard mask and the magnetic tunnel junction stack, selectively removing a portion of the dielectric surrounding the metallic hard mark.

A spin-orbit torque type magnetoresistance effect element including a magnetoresistance effect element having a first ferromagnetic metal layer with a fixed magnetization direction, a second ferromagnetic metal layer with a varying magnetization direction, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer; and spin-orbit torque wiring that extends in a first direction intersecting with a stacking direction of the magnetoresistance effect element and that is joined to the second ferromagnetic metal layer; wherein the magnetization of the second ferromagnetic metal layer is oriented in the stacking direction of the magnetoresistance effect element; and the second ferromagnetic metal layer has shape anisotropy, such that a length along the first direction is greater than a length along a second direction orthogonal to the first direction and to the stacking direction.

A spin-orbit-torque magnetization rotational element includes: a spin-orbit torque wiring layer which extends in an X direction; and a first ferromagnetic layer which is laminated on the spin-orbit torque wiring layer, wherein the first ferromagnetic layer has shape anisotropy and has a major axis in a Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends, and wherein the easy axis of magnetization of the first ferromagnetic layer is inclined with respect to the X direction and the Y direction orthogonal to the X direction on a plane in which the spin-orbit torque wiring layer extends.

A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

Some embodiments relate to a probabilistic random number generator. The probabilistic random number generator includes a memory cell comprising a magnetic tunnel junction (MTJ), and an access transistor coupled to the MTJ of the memory cell. A variable current source is coupled to the access transistor and is configured to provide a plurality of predetermined current pulse shapes, respectively, to the MTJ to generate a bit stream that includes a plurality of probabilistic random bits, respectively, from the MTJ. The predetermined current pulse shapes have different current amplitudes and/or pulse widths corresponding to different switching probabilities for the MTJ.

A film stack for a magnetic tunnel comprises a substrate, a magnetic reference layer disposed over the substrate, and a tunnel barrier layer disposed over the magnetic reference layer. The film stack further comprises a magnetic storage layer disposed over the tunnel barrier layer, and a capping layer disposed over the magnetic storage layer. Further, the film stack comprises at least one protection layer disposed between the magnetic reference layer and the tunnel barrier layer and disposed between the magnetic storage layer and the capping layer. Additionally, a material forming the at least one protection layer differs from at least one of a material forming the magnetic reference layer and a material forming the magnetic storage layer.

A magnetoresistive stack includes a reference layer including a magnetic layer, an antiferromagnetic layer in exchange coupling with the magnetic layer, a magnetic layer substantially of the same magnetisation as the magnetic layer, a spacer layer between the magnetic layers with a thickness for enabling an antiferromagnetic coupling between the magnetic layers of a first coupling intensity, a free layer having a coercivity of less than 10 microTesla, the free layer including a magnetic layer, an antiferromagnetic layer in exchange coupling with the magnetic layer, a magnetic layer substantially of the same magnetisation as the magnetic layer, a spacer layer between the magnetic layers with a thickness for enabling an antiferromagnetic coupling between the magnetic layers of a second coupling intensity lower than the first coupling intensity, a third spacer layer separating the reference and free layers.

Provided is a magnetoresistive random-access memory (MRAM) cell. The MRAM cell comprises a top contact, a hard mask layer below the top contact, and a magnetic tunnel junction (MTJ) below the hard mask layer. The MRAM cell further comprises a diffusion barrier below the MTJ, a bottom contact below the diffusion barrier, and a magnetic liner arranged around the bottom contact.