Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

In accordance with embodiments disclosed herein, there are provided methods and systems for implementing damage-and-resist-free laser patterning of dielectric films on textured silicon. For example, in one embodiment, such means include means for depositing a Silicon nitride (SiNx) or SiOx (silicon oxide) layer onto a crystalline silicon (c-Si) substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) processing; depositing an amorphous silicon (a-Si) film on top of the SiNx or SiOx layer; patterning the a-Si film to define an etch mask for the SiNx or SiOx layer; removing the SiNx or SiOx layer via a Buffered Oxide Etch (BOE) chemical etch to expose the c-Si surface; removing the a-Si mask with a hydrogen plasma etch in a PECVD tool to prevent current loss from the mask; and plating the exposed c-Si surface with metal contacts. Other related embodiments are disclosed.

A photodetector includes an insulating layer on a substrate, a first graphene layer on the insulating layer, a 2-dimensional (2D) material layer on the first graphene layer, a second graphene layer on the 2D material layer, a first electrode on the first graphene layer, and a second electrode on the second graphene layer. The 2D material layer includes a barrier layer and a light absorption layer. The barrier layer has a larger bandgap than the light absorption layer.

Methods of fabricating solar cells using a metal-containing thermal and diffusion barrier layer in foil-based metallization approaches, and the resulting solar cells, are described. For example, a method of fabricating a solar cell includes forming a plurality of semiconductor regions in or above a substrate. The method also includes forming a metal-containing thermal and diffusion barrier layer above the plurality of semiconductor regions. The method also includes forming a metal seed layer on the metal-containing thermal and diffusion barrier layer. The method also includes forming a metal conductor layer on the metal seed layer. The method also includes laser welding the metal conductor layer to the metal seed layer. The metal-containing thermal and diffusion barrier layer protects the plurality of semiconductor regions during the laser welding.

An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.

An optical semiconductor device comprises, on a substrate, a fin of diamond-cubic semiconductor material and, at the base of the fin, a slab of that semiconductor material, in a diamond-hexagonal structure, that extends over the full width of the fin, the slab being configured as an optically active material. This semiconductor material can contain silicon. A method for manufacturing the optical semiconductor device comprises annealing the sidewalls of the fin, thereby inducing a stress gradient along the width of the fin.

Thin-film photovoltaic devices and methods of their use and manufacture are disclosed. More particularly, polycrystalline CuIn.sub.(1-x)Ga.sub.xSe.sub.2 (CIGS) based thin-film photovoltaic devices having independently tunable sublayers are disclosed. Also provided are methods of producing an n-doped graphene.

The present disclosure relates to a solid state imaging element and an electronic device that make it possible to improve sensitivity to light on a long wavelength side. A solid state imaging element according to a first aspect of the present disclosure has a solid state imaging element in which a large number of pixels are arranged vertically and horizontally, the solid state imaging element includes a periodic concave-convex pattern on a light receiving surface and an opposite surface to the light receiving surface of a light absorbing layer as a light detecting element. The present disclosure can be applied to, for example, a CMOS and the like installed in a sensor that needs a high sensitivity to light belonging to a region on the long wavelength side, such as light in the infrared region.

The present technology relates to a solid-state imaging apparatus, a manufacturing method therefor, and an electronic apparatus by which fine pixel signals can be suitably generated.

A charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges, a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section, and a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section are provided. A bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor.

A chipset with light energy harvester, includes a substrate, a functional element layer, and a light energy harvesting layer, both are stacked vertically on the substrate, and an interconnects connected between the functional element layer and the light energy harvesting layer.