A controller, for use in a storage device of a data processing system, includes a host interface, a memory interface and one or more processors. The host interface is configured to communicate over a computer network with one or more remote hosts of a data processing system. The memory interface is configured to communicate locally with a non-volatile memory of the storage device. The one or more processors are configured to manage local storage or retrieval of media objects at the non-volatile memory, and to perform additional tasks that are not associated with management of storage or retrieval of the objects.

Embodiments described herein provide improved methods and systems for generating metadata for media objects at a computational engine (such as an artificial intelligence engine) within the storage edge controller, and for storing and using such metadata, in data processing systems.

A storage control device coupled to a storage device and located remotely from a host device receives media object data from the host device. The storage control device identifies a type of the media object data and select, based on the identified type, a computational model from among a plurality of computational models for use by a computational engine of the storage control device. The computational engine uses the selected computational model to generate metadata describing the media object data. The metadata is stored in the storage device so as to be selectively retrievable from the storage device separately from the media object data.

A method and system are disclosed for handling a received content word in a system comprising a memory of memory words, wherein: each memory word comprises Bloom Filter structures. The method comprises hashing the content word into a fixed-size word, pointing to the memory word corresponding to an address of the fixed-size word, pointing to, and reading, the Bloom Filter structure in the pointed memory word corresponding to an address in the fixed-size word, and reading and writing the content of the Bloom Filter structures so as to keep track of a number of occurrences of the received content word over a sliding window of time.

A circuit includes a buffer configured to receive a first Flexible Ethernet (FlexE) frame having 66b blocks including 66b overhead blocks and 66b data blocks, wherein the buffer is configured to accumulate the 66b overhead blocks and the 66b data blocks; a mapping circuit configured to map four x 66b overhead blocks from the buffer into a 257b overhead block and to map a sequence of four x 66b data blocks from the buffer into a 257b data block; and a transmit circuit configured to transmit a second FlexE frame having 257b blocks from the mapping circuit. The mapping circuit can be configured to accumulate four 66b blocks of a same kind from the buffer for mapping into a 257b block, where the same kind is one of overhead and a particular calendar slot n where n=0-19.

Some embodiments use one or more FPGAs and external memories associated with the FPGAs to implement large, hash-addressable tables for a data plane circuit. These embodiments configure at least one message processing stage of the DP circuit to store (1) a first plurality of records for matching with a set of data messages received by the DP circuit, and (2) a redirection record redirecting data messages that do not match the first plurality of records to a DP egress port associated with the memory circuit. These embodiments configure an external memory circuit to store a larger, second set of records for matching with redirected data messages received through the DP egress port associated with the memory circuit. This external memory circuit is a hash-addressable memory in some embodiments. To determine whether a redirected data message matches a record in the second set of record, the method of some embodiments configures an FPGA associated with the hash-addressable external memory to use a collision free hash process to generate a collision-free, hash address value from a set of attributes of the data message. This hash address value specifies an address in the external memory for the record in the second set of records to compare with the redirected data message.

In a recording device, a data memory including a DRAM having a write pointer for each of banks, and a queue control memory that stores an active flag is provided. When frame data is written into a write-target queue, a bank for which an active flag indicates an activated state is selected as a write-target bank among the banks to write the frame data, and if there is no bank for which an active flag indicates an activated state, a bank for which an active flag indicates a deactivated state is selected as a write-target bank, a row address of a write pointer of the bank is activated, and thereafter the frame data is written.

A controller, for use in a storage device of a data processing system, includes a host interface, a memory interface and one or more processors. The host interface is configured to communicate over a computer network with one or more remote hosts of a data processing system. The memory interface is configured to communicate locally with a non-volatile memory of the storage device. The one or more processors are configured to manage local storage or retrieval of media objects at the non-volatile memory, and to selectively compute metadata that defines content characteristics of media objects that are stored, or that are to be stored, in the non-volatile memory.

A network switch includes a plurality of ports each connected to a network or a terminal. The network switch performs routing between the plurality of ports. A control device is apart from the network switch. The control device controls the network switch. The network switch includes a command storage unit. The command storage unit stores a plurality of commands acquired from the control device for physical devices.

Implementations of this disclosure provide data transmission operations and network interface controllers. An example method performed by a first RDMA network interface controller includes obtaining m data packets from a host memory of a first host; sending the m data packets to a second RDMA network interface controller of a second host; backing up the m data packets to a network interface controller memory integrated into the first RDMA network interface controller; determining that the second RDMA network interface controller does not receive n data packets of the m data packets; and in response, obtaining the n data packets from the m data packets that have been backed up to the network interface controller memory integrated into the first RDMA network interface controller, and retransmitting the n data packets to the second RDMA network interface controller.