A semiconductor device includes a layered structure forming multiple carrier channels including at least one n-type channel formed in a first layer made of a first material and at least one p-type channel formed in a second layer made of a second material and a set of electrodes for providing and controlling carrier charge in the carrier channels. The first material is different than the second material, and the first and the second materials are selected such that the n-type channel and the p-type channel have comparable switching frequency and current capability.

A HEMT cell includes two or more gallium nitride (GaN) high-electron-mobility transistor (HEMT) devices electrically connected in series with each other. The HEMT cell includes a HEMT cell drain, a HEMT cell source, and a HEMT cell gate. The HEMT cell drain connects with the drain of a first GaN HEMT device in the series. The HEMT cell source connects with the source of a last GaN HEMT device in the series. The HEMT cell gate connects to a first two-dimensional electron gas (2DEG) gate bias resistor that connects with the gate of the first GaN HEMT device. The HEMT cell gate connects to a second 2DEG gate bias resistor that connects with the gate of the second GaN HEMT device. The first and second 2DEG gate bias resistors are located in a 2DEG layer of the HEMT cell. A multi-throw RF switch is also disclosed.

A semiconductor device that can be miniaturized or highly integrated can be provided. The semiconductor device includes a first conductor positioned over a substrate; an oxide positioned in contact with atop surface of the first conductor; a second conductor, a third conductor, and a fourth conductor positioned over the oxide; a first insulator in which a first opening and a second opening are formed, the first insulator being positioned over the second conductor to the fourth conductor; a second insulator positioned in the first opening; a fifth conductor positioned over the second insulator; a third insulator positioned in the second opening; and a sixth conductor positioned over the third insulator. The third conductor is positioned to overlap with the first conductor. The first opening is formed to overlap with a region between the second conductor and the third conductor. The second opening is formed to overlap with a region between the third conductor and the fourth conductor.

Method for fabricating a semiconductor structure. The semiconductor structure includes: a crystalline silicon substrate; a dielectric layer on the crystalline silicon substrate, the opening having an opening with sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; and a crystalline compound semiconductor layer thereby forming a processable crystalline compound semiconductor substrate, wherein the bottom of the opening is isolated from the crystalline compound material.

A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

A method includes forming a first semiconductor fin, and oxidizing surface portions of the first semiconductor fin to form a first oxide layer. The first oxide layer includes a top portion overlapping the first semiconductor fin and sidewall portions on sidewalls of the first semiconductor fin. The top portion of the first oxide layer is then removed, wherein the sidewall portions of the first oxide layer remains after the removing. The top portion of the first semiconductor fin is removed to form a recess between the sidewall portions of the first oxide layer. An epitaxy is performed to grow a semiconductor region in the recess.

A semiconductor device that includes transistors with different threshold voltages is provided. Alternatively, a semiconductor device including a plurality of kinds of circuits and transistors whose electrical characteristics are different between the circuits is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes an oxide semiconductor, a conductor, a first insulator, a second insulator, and a third insulator. The conductor has a region where the conductor and the oxide semiconductor overlap with each other. The first insulator is positioned between the conductor and the oxide semiconductor. The second insulator is positioned between the conductor and the first insulator. The third insulator is positioned between the conductor and the second insulator. The second insulator has a negatively charged region.

A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.

A semiconductor device or the like capable of preventing malfunction of a driver circuit is provided. In a driver circuit for driving a power device used for current supply, a transistor including an oxide semiconductor is used as a transistor in a circuit (specifically, for example, a level shift circuit) requiring a high withstand voltage. In addition, a transistor (for example, a silicon transistor or the like) capable of higher operation than a transistor including an oxide semiconductor is preferably used as a transistor in a circuit (specifically, for example, a buffer circuit, a flip-flop circuit, or the like) requiring a lower withstand voltage than the level shift circuit.

A method of cutting a wafer by irradiating the wafer with laser energy, comprises emitting a sequence of successive laser beam pulses having a first set of laser beam pulses and a second set of laser beam pulses, the first set of laser beam pulses comprising: laser beam pulses having respective pulse widths in the range from 0.1 to 300 nanoseconds, or a plurality of bursts of laser beam pulses having an inter-burst spacing in the range from 0.1 to 100 nanoseconds, each pulse within the bursts having a pulse width of 100 picoseconds or less, and the second set of laser beam pulses comprising laser beam pulses having pulse widths of 100 picoseconds or less.