The techniques described herein relate to a transistor including a single crystal substrate, an epitaxial channel layer (ECL) on the single crystal substrate, a gate layer on the ECL, a source electrical contact coupled to the ECL, a drain electrical contact coupled to the ECL, and a gate electrical contact coupled to the gate layer. The substrate includes a substrate material with a first crystal symmetry and the ECL includes an ECL oxide material with a second crystal symmetry, where the first crystal symmetry is different from the second crystal symmetry. The gate layer includes a gate oxide material, where the ECL oxide material has a first bandgap and the gate oxide material has a second bandgap, and the second bandgap is wider than the first bandgap.

Devices and methods of manufacturing light emitting devices including selective area epitaxy deposited N-polar semiconductors. The devices and methods can be utilized to realize high-quality, high-performance and/or high-efficiency nanowire based light emitting devices.

A light-emitting element includes a first semiconductor layer doped to have a first polarity; a second semiconductor layer doped to have a second polarity that is different from the first polarity; an active layer placed between the first semiconductor layer and the second semiconductor layer; and an insulating layer surrounding at least the outer surface of the active material. The insulating layer includes an insulating film surrounding the active layer, and an element dispersion agent including a magnetic metal and bonded to an outer surface of the insulating film.

There is a method for forming a semiconductor nanostructure on a substrate. The method includes placing a substrate and a semiconductor material in a pulsed laser deposition chamber; selecting parameters including a fluence of a laser beam, a pressure P inside the chamber, a temperature T of the substrate, a distance d between the semiconductor material and the substrate, and a gas molecule diameter a.sub.0 of a gas to be placed inside the chamber so that conditions for a Stranski-Krastanov nucleation are created; and applying the laser beam with the selected fluence to the semiconductor material to form a plume of the semiconductor material. The selected parameters determine the formation, from the plume, of (1) a nanolayer that covers the substrate, (2) a polycrystalline wetting layer over the nanolayer, and (3) a single-crystal nanofeature over the polycrystalline wetting layer, and the single-crystal nanofeature is grown free of any catalyst or seeding layer.

A nitride semiconductor ultraviolet light-emitting element is provided. The element includes a light-emitting element with n-type, active, and p-type layers stacked vertically and made of AlGaN-based wurtzite structured semiconductors. The active layer has a quantum-well structure and each layer is epitaxially grown having a surface on which multi-step terraces parallel to the (0001) plane are formed. The n-type layer has a stratiform regions with locally lower AlN mole fraction which is inclined with respect to an upper surface of the n-type layer. The p-type layer has a lowermost electron blocking layer and an uppermost contact layer. Each semiconductor layer in the active layer and the electron blocking layer have inclined regions with respect to the (0001) plane connecting adjacent terraces of the multi-step terraces, and terrace regions other than inclined regions. An AlN mole fraction of the terrace regions in the electron blocking layer is between 69% and 89%, inclusive.

A nitride semiconductor ultraviolet light-emitting element is provided. The element includes a light-emitting element with n-type, active, and p-type layers stacked vertically and made of AlGaN-based wurtzite structured semiconductors. The active layer has a quantum-well structure and each layer is epitaxially grown having a surface on which multi-step terraces parallel to the (0001) plane are formed. The n-type layer has a stratiform regions with locally lower AlN mole fraction which is inclined with respect to an upper surface of the n-type layer. The p-type layer has a lowermost electron blocking layer and an uppermost contact layer. Each semiconductor layer in the active layer and the electron blocking layer have inclined regions with respect to the (0001) plane connecting adjacent terraces of the multi-step terraces, and terrace regions other than inclined regions. An AlN mole fraction of the terrace regions in the electron blocking layer is between 69% and 89%, inclusive.

A nitride semiconductor ultraviolet light-emitting element is provided. The element includes a light-emitting element structure part with an n-type layer, an active layer, and a p-type layer stacked vertically, which are made of AlGaN-based semiconductors with wurtzite structure. The n-type layer has an n-type AlGaN-based semiconductor, the active layer has well layers including an AlGaN based semiconductor, and the p-type layer has a p-type AlGaN-based semiconductor. Each semiconductor layer in the n-type and the active layers is an epitaxially grown layer having a surface on which multi-step terraces parallel to the (0001) plane are formed. The n-type layer has first Ga-rich regions which include n-type AlGaN regions in which an AlGaN composition ratio is an integer ratio of Al.sub.1Ga.sub.1N.sub.2. The well layer includes a second Ga-rich region, which includes an AlGaN region in which an AlGaN composition ratio is an integer ratio of Al.sub.1Ga.sub.2N.sub.3.

A nitride semiconductor ultraviolet light-emitting element is provided. The element includes a light-emitting element structure part with an n-type layer, an active layer, and a p-type layer stacked vertically, which are made of AlGaN-based semiconductors with wurtzite structure. The n-type layer has an n-type AlGaN-based semiconductor, the active layer has well layers including an AlGaN based semiconductor, and the p-type layer has a p-type AlGaN-based semiconductor. Each semiconductor layer in the n-type and the active layers is an epitaxially grown layer having a surface on which multi-step terraces parallel to the (0001) plane are formed. The n-type layer has first Ga-rich regions which include n-type AlGaN regions in which an AlGaN composition ratio is an integer ratio of Al.sub.1Ga.sub.1N.sub.2. The well layer includes a second Ga-rich region, which includes an AlGaN region in which an AlGaN composition ratio is an integer ratio of Al.sub.1Ga.sub.2N.sub.3.

The techniques described herein relate to a transistor, including a substrate, an epitaxial buffer layer, an epitaxial channel layer, and a gate layer. The substrate includes a first oxide material with a first crystal symmetry, the epitaxial buffer layer includes a second oxide material with a second crystal symmetry, the epitaxial channel layer includes a third oxide material with a third crystal symmetry and a first bandgap, and the gate layer includes a fourth oxide material with a second bandgap. The first crystal symmetry is different from either the second crystal symmetry or the third crystal symmetry, and the second bandgap is wider than the first bandgap. The transistor also includes electrical contacts including a source electrical contact coupled to the epitaxial channel layer, a drain electrical contact coupled to the epitaxial channel layer, and a gate electrical contact coupled to the gate layer.

The techniques described herein relate to a transistor, including a substrate, an epitaxial buffer layer, an epitaxial channel layer, and a gate layer. The substrate includes a first oxide material with a first crystal symmetry, the epitaxial buffer layer includes a second oxide material with a second crystal symmetry, the epitaxial channel layer includes a third oxide material with a third crystal symmetry and a first bandgap, and the gate layer includes a fourth oxide material with a second bandgap. The first crystal symmetry is different from either the second crystal symmetry or the third crystal symmetry, and the second bandgap is wider than the first bandgap. The transistor also includes electrical contacts including a source electrical contact coupled to the epitaxial channel layer, a drain electrical contact coupled to the epitaxial channel layer, and a gate electrical contact coupled to the gate layer.