Example methods, compositions and structures are presented whereby sub-10-nm-thick strain-relieving Si.sub.1-xGe.sub.x layers can be realized by Ge ion implantation, into, and selective oxidation of, Si(111) wafers. The resulting Ge-rich layers are fully strain relaxed via a network of misfit dislocations at the Si/Si.sub.1-xGe, interface, which do not propagate through the Si.sub.1-xGe.sub.x film. The dislocation network has been found to coincide with a periodic variation in the composition at the Si/Si.sub.1-xGe.sub.x interface and is believed to result from the defect-medicated diffusion of Si atoms from the Si substrate through the Si.sub.1-xGe.sub.x layer to the above SiO.sub.2 layer. The epitaxial growth of GaAs on such ultra-thin substrates is demonstrated, presenting a promising approach for solving the long-standing challenge of local, monolithic integration of III-V optoelectronics on the Si platform.

Example methods, compositions and structures are presented whereby sub-10-nm-thick strain-relieving Si.sub.1-xGe.sub.x layers can be realized by Ge ion implantation, into, and selective oxidation of, Si(111) wafers. The resulting Ge-rich layers are fully strain relaxed via a network of misfit dislocations at the Si/Si.sub.1-xGe, interface, which do not propagate through the Si.sub.1-xGe.sub.x film. The dislocation network has been found to coincide with a periodic variation in the composition at the Si/Si.sub.1-xGe.sub.x interface and is believed to result from the defect-medicated diffusion of Si atoms from the Si substrate through the Si.sub.1-xGe.sub.x layer to the above SiO.sub.2 layer. The epitaxial growth of GaAs on such ultra-thin substrates is demonstrated, presenting a promising approach for solving the long-standing challenge of local, monolithic integration of III-V optoelectronics on the Si platform.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a gate oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a gate oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.

Provided are a light emitting device, a method for manufacturing same, and a display device including the light emitting device. The method for manufacturing the light emitting device comprises: preparing a lower substrate including a substrate and a buffer semiconductor layer on the substrate, forming an element rod by forming a separating layer on the lower substrate, forming a first conductivity type semiconductor layer, an active material layer, and a second conductivity type semiconductor layer on the separating layer, and etching the first conductivity type semiconductor layer, the active material layer, the second conductivity type semiconductor layer, and the separating layer in a direction perpendicular to the lower substrate, forming a first insulating layer surrounding an outer circumferential surface of the element rod, forming a second insulating layer surrounding an outer circumferential surface of the first insulating layer and separating the element rod from the lower substrate.

A display device is provided. The display device includes a plurality of pixels disposed in a display area, each of the plurality of pixels includes a first electrode and a second electrode spaced apart from each other in a first direction, and at least one light emitting element disposed between the first electrode and the second electrode and electrically connected to the first electrode and the second electrode, and a distance in the first direction between one end of the light emitting element and one end of the second electrode is greater than a distance in the first direction between another end of the light emitting element and one end of the first electrode.

The invention relates to various aspects of a -LED or a -LED array for augmented reality or lighting applications, in particular in the automotive field. The -LED is characterized by particularly small dimensions in the range of a few m.

A display device may include first signal lines arranged in a display area, and extending in a first direction, pixels arranged in the display area, and respectively connected to the first signal lines, first pads located in a first pad area at a side of the display area in the first direction, and arranged along a second direction, first lines extending along the first direction to the display area from the first pad area, and respectively connected to the first pads, and second lines arranged in the display area, and respectively connecting the first lines to the first signal lines, wherein the display area includes a first sub-display area corresponding to the first pad area, and a second sub-display area adjacent the first sub-display area, and wherein the first lines are arranged only in the first sub-display area among the first and second sub-display areas.

A semiconductor structure includes a superlattice with two or more unit cells, wherein each of the unit cells includes: a first epitaxial layer including NiO; and a second epitaxial layer including a second epitaxial oxide material. In some cases, the semiconductor structure can include: a first region including p-type conductivity, wherein the first region includes the superlattice; a second region including an epitaxial oxide material; and a third region including an epitaxial oxide material, wherein the second region is located between the first region and the third region along a growth direction.

A semiconductor structure includes a superlattice with two or more unit cells, wherein each of the unit cells includes: a first epitaxial layer including NiO; and a second epitaxial layer including a second epitaxial oxide material. In some cases, the semiconductor structure can include: a first region including p-type conductivity, wherein the first region includes the superlattice; a second region including an epitaxial oxide material; and a third region including an epitaxial oxide material, wherein the second region is located between the first region and the third region along a growth direction.