Patent classifications
H04L9/28
Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a one round pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
Secure data transmission using quantum communication
Methods and systems for transmitting data are described. A random data stream is generated. A data stream is generated comprising the random data stream and indicators as to which data of the random data stream is valid data to be communicated to a recipient. The random data stream and/or the data stream may be communicated using quantum entanglement.
Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a one round pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a one round pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a one round pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a one round pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
Information processing apparatus, method for processing information, and medium
An information processing apparatus for encrypting or decrypting data by AES scheme, includes a processor; and a memory storing a first table including mixed components based on exclusive OR of first random components and key data, a second table, and a third table. The processor executes selecting four bytes of sub-round data from the data; a first transformation based on the first table, for each of one-byte data items of the sub-round data, to generate first data by taking exclusive OR of the one-byte data items and the mixed components; a second transformation based on the second table to transform the first data into second data; a third transformation based on the third table to transform the second data into multiple items of third data; calculating exclusive OR of the third data.
SMS4 acceleration processors having round constant generation
A processing system includes a memory and a processing logic operatively coupled to the memory. The processing logic identifies one or more constant bits of an output bit sequence. The processing logic generates a plurality of variable bits of the output bit sequence. The processing logic produces the output bit sequence including the identified constant bits and the generated plurality of variable bits.
Operator lifting in cryptographic algorithm
A system for performing an operation on data using obfuscated representations of the data is disclosed. Obtaining means are configured to obtain a first obfuscated representation of a first data value and obtain a second obfuscated representation of a second data value. A determining means 102 is configured to determine an obfuscated representation of a third data value, by performing the corresponding operations on the obfuscated representation of the first data value and the obfuscated representation of the second data value. Obfuscating means 101 may be configured to generate the first obfuscated representation based on the first data value and generate the second obfuscated representation based on the second data value. De-obfuscating means 103 may be configured to de-obfuscate the obfuscated representation of the third data value in order to obtain the third data value using a system of equations.
Security improvements for tickets
A method of validating the authenticity of a ticket including a unique ticket identifier generated at an issuing terminal in accordance with a confidential algorithm is provided. The method includes receiving one or more identification variable values expressed with respect to a first coordinate measurement domain, the one or more identification variable values enabling the location of ticket verification information within the unique ticket identifier to be determined, using a coordinate transform function configured to map coordinate values from the first coordinate measurement domain to a second coordinate measurement domain to calculate one or more values of the one or more received identification variable values with respect to the second coordinate measurement domain, extracting the verification information from the unique ticket identifier on the basis of the calculated identification variable values, and verifying the authenticity of the ticket on the basis of the extracted verification information.