A process for the production of high-speed and high-voltage transistors includes implementing a masked first and/or second ion implantation in active areas of a substrate for forming a collector area of the first conductivity type, depositing an insulator layer on a surface of the substrate and defining collector windows, depositing a buffer layer in the collector windows and a base layer of a second conductivity type, depositing an insulator layer over a cap layer of the buffer layer, implementing ions of a same doping type as the collector of the transistor, depositing a silicon layer and forming a base-emitter spacer within the emitter window, exposing a surface of the emitter window, performing epitaxial deposition of a emitter layer of the first conductivity type, depositing of an insulator layer, exposing the cap layer, and patterning parts of the buffer layer, the base layer and the cap layer.

The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a bipolar junction transistor (BJT), a field effect transistor (FET), and a composite structure. The semiconductor substrate includes a BJT region, a complementary FET (CFET) region, and a transition region between the BJT region and the CFET region. The BJT is on the semiconductor substrate in the BJT region. The FET is on the semiconductor substrate in the CFET region. The composite structure is on the semiconductor substrate in the transition region. The composite structure includes a dielectric material. The dielectric material has a sidewall proximate and facing the CFET region and has a top surface that forms at least a portion of an upper surface of the composite structure.

In a semiconductor device, on a surface of a collector layer including a compound semiconductor of a first conductor type, facing in a first direction, a base layer including a compound semiconductor of a second conductor type opposite from the first conductor type is disposed. On a partial region of a surface of the base layer facing in the first direction, at least one emitter mesa including a compound semiconductor of the first conductor type and forming a heterojunction with the base layer is disposed. A collector electrode is on a surface of the collector layer facing in a second direction opposite to the first direction. An emitter electrode is on a surface of the emitter mesa facing in the first direction. A base electrode is on a region, in the surface of the base layer facing in the first direction, on which the emitter mesa is not disposed.

In a semiconductor device, on a surface of an emitter layer including a compound semiconductor of a first conductor type, facing in a first direction, a base layer including a compound semiconductor of a second conductor type opposite from the first conductor type and subjected to heterojunction to the emitter layer is disposed. At least one collector mesa including a compound semiconductor of the first conductor type is disposed on a surface of the base layer facing in the first direction. An emitter electrode is disposed on a surface of the emitter layer facing in a second direction opposite to the first direction. A base electrode continuously surrounding the collector mesa in plan view is disposed on the surface of the base layer facing in the first direction. A collector electrode is disposed on a surface of the collector mesa facing in the first direction.

Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a substrate having a top surface, a trench isolation region in the substrate, and a base layer on the top surface of the substrate. The base layer extending across the trench isolation region. A first bipolar junction transistor includes a first collector in the substrate and a first emitter on a first portion of the first base layer. The first portion of the first base layer is positioned between the first collector and the first emitter. A second bipolar junction transistor includes a second collector in the substrate and a second emitter on a second portion of the first base layer. The second portion of the first base layer is positioned between the second collector and the second emitter.

This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having retrograde doping concentration in the collector. One aspect of this disclosure is a bipolar transistor that includes a collector having a retrograde doping profile in which a doping concentration is highest at a junction of the base and the collector and decreases through a portion of the collector to about 95% less to about 99.5% less. Such bipolar transistors can be implemented, for example, in power amplifiers.

The present disclosure relates to semiconductor structures and, more particularly, to vertical heterojunction bipolar transistors and methods of manufacture. The structure includes: a collector region above a semiconductor substrate; a base region above the collector region; an emitter region adjacent to the base region; and an undercut structure above the semiconductor substrate and adjacent to the collector region.

The present disclosure relates to semiconductor structures and, more particularly, to vertical heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; a base region above the collector region; an emitter region over a portion of the base region; and an undercut region bounded vertically and laterally by the base region and adjacent to the emitter region.

A semiconductor device includes a semiconductor substrate, a collector region having a first width formed within the semiconductor substrate and an intrinsic base region having a second width, disposed over the collector region, wherein the first width is greater than the second width. An extrinsic base region having an upper surface is formed over the collector region and electrically coupled to the intrinsic base region, wherein the extrinsic base region includes a monocrystalline region coupled to the intrinsic base region and a polycrystalline region coupled to the monocrystalline region. An emitter region is formed over the base region.

A semiconductor structure and a method for forming same. The semiconductor structure comprises: a substrate, which comprises a first region; two or more capacitor structures, which are connected in parallel and are sequentially stacked on the first region in the direction perpendicular to the substrate, wherein a top edge region of at least one capacitor structure is provided with a protective layer, the protective layer being used for covering the top edge region of the capacitor structure, and thereby reducing the current which flows from a metal layer, which is located above the protective layer, to the edge region of the capacitor structure. By using the scheme, the capacity of a capacitor structure in a semiconductor structure can be increased without increasing the area of a device, and the reliability of the capacitor structure can be improved.