A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.

A semiconductor device and a process to form the same are disclosed. The semiconductor device includes a support, an active semiconductor stack including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer, the first to third semiconductor layers being sequentially stacked on the support, and an electrode on the third semiconductor layer. The first semiconductor layer and the second semiconductor layer provide a buried region in a portion under the electrode, the buried region being filled with a material having a first dielectric constant smaller than a second dielectric constant of the first semiconductor layer and a third dielectric constant of the second semiconductor layer.

According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon.

The disclosure describes the use of strain to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition

Methods of manufacture of advanced electronic and photonic structures including heterojunction transistors, transistor lasers and solar cells and their related structures, are described herein. Other embodiments are also disclosed herein.

One aspect of this disclosure is a power amplifier module that includes a power amplifier; a wire bond pad electrically connected to the power amplifier, the wire bond pad including a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer; and a conductive trace having a top surface with a plated portion and an unplated portion surrounding the plated portion, the wire bond pad being disposed over the plated portion. Other embodiments of the module are provided along with related methods and components thereof.

A heterojunction bipolar transistor (HBT) amplifier device includes transistor fingers arranged in parallel on a substrate. Each transistor finger includes a base/collector mesa stripe shaving a trapezoidal shaped cross-section with sloping sides, and having a base stacked on a collector; a set of emitter mesa stripes arranged on the base/collector mesa stripe; and emitter metallization formed over the set of emitter mesa stripes and the base/collector mesa. The emitter metallization includes a center portion for providing electrical and thermal connectivity to the emitter mesa stripes and extended portions extending beyond the base and overlapping onto the sloping sides of the base/collector mesa stripe for increasing thermal coupling to the collector. A common conductive pillar is formed over the transistor fingers for providing electrical and thermal conductivity. Also, thermal shunts are disposed on the substrate between adjacent transistor fingers, where the thermal shunts are electrically isolated from the transistor fingers.

Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.

A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.