Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed on the first semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the substrate are etched to define first and second emitter fingers from the second semiconductor layer and trenches in the substrate that are laterally positioned between the first and second emitter fingers. The first semiconductor layer may function as a base layer in the device structure.

This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at a doping spike in the collector. The doping spike can be disposed relatively near an interface between the collector and the base. For instance, the doping spike can be disposed within half of the thickness of the collector from the interface between the collector and the base. Such bipolar transistors can be implemented, for example, in power amplifiers.

A semiconductor device includes a heterojunction bipolar transistor (HBT) having a collector, a base, and an emitter. The base includes a monocrystalline base layer, including silicon-germanium, on the collector, and an extrinsic base layer, including polycrystalline silicon, extending partway over the monocrystalline base layer. The base further includes a base link, including polycrystalline silicon-germanium, connecting the monocrystalline base layer to the extrinsic base layer. An emitter spacer, of dielectric material, laterally separates the emitter from the extrinsic base layer. The HBT has a spacer-extrinsic base vertical offset between a bottom of the emitter spacer and a bottom surface of the extrinsic base layer adjacent to the emitter spacer. The emitter spacer has a bottom width at a bottom of the emitter spacer. A sum of the spacer-extrinsic base vertical offset and the bottom width of the emitter spacer is greater than the thickness of the monocrystalline base layer.

The present disclosure provides a full-reflection display substrate, a manufacturing method thereof and a full-reflection display device. The full-reflection display substrate includes: a base substrate, the base substrate including a display region and a non-display region; a signal line arranged in the display region; a bonding pin arranged in the non-display region, coupled to the signal line and bonded to a driving circuitry; a reflection layer arranged in the display region; and an etch stop pattern arranged at a same layer and made of a same material as the reflection layer, arranged in the non-display region, and at least covering a side surface of the bonding pin.

The present disclosure relates to semiconductor structures and, more particularly, to vertical heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base above the collector region; an emitter above the intrinsic base region; and an extrinsic base on the intrinsic base and adjacent to the emitter, wherein the collector region includes an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the base region.

The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a pedestal dielectric layer, a collector layer, a base layer, and an emitter layer. The semiconductor substrate includes a bipolar junction transistor region. The pedestal dielectric layer is in the bipolar junction transistor region and is over an upper surface of the semiconductor substrate. The collector layer is on the upper surface of the semiconductor substrate and is through the pedestal dielectric layer. The base layer is on the collector layer and an upper surface of the pedestal dielectric layer. The pedestal dielectric layer extends laterally over the upper surface of the semiconductor substrate from the base layer. The emitter layer is on the base layer.

A display device may include: a base layer including a display area and a non-display area; and a plurality of pixels provided on the display area, and each including a plurality of sub-pixels. Each of the sub-pixels may include a pixel circuit layer, and a display element layer including an emission area formed to emit light, and a non-emission area provided around a perimeter of the emission area. The display element layer may include: a partition wall provided on the emission area of each of the sub-pixels; a bank provided on the non-emission area of each sub-pixel, and disposed on a surface equal to a surface on which the partition wall is disposed; a first electrode and a second electrode provided on the partition wall and spaced apart from each other; and at least one light emitting element provided between the first and second electrodes in the emission area of each sub-pixel, and configured to emit the light.

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region; an extrinsic base comprising an emitter opening with an angled sidewall; an emitter within the emitter opening; and an intrinsic base between the emitter and the collector.

A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having increased collector thickness for improved ruggedness. In some embodiments, the collector thickness can be above 1.1 microns. The collector can have at least one doping concentration grading. The collector can have a high doping concentration at a junction between the collector and the sub-collector, such as at the high end of the grading. In some embodiments, the high doping concentration can be above about 910.sup.16 cm.sup.3. The collector can include a region with high doping concentration adjacent the base. The collector can include a discontinuity in the doping concentration, such as at the low end of the grading. Such bipolar transistors can be implemented, for example, in power amplifiers.