The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

A structure including a first emitter-collector (E/C) layer over a substrate. The structure further includes an intrinsic base layer over the first E/C layer and a second E/C layer over the intrinsic base layer. The structure includes an extrinsic base layer on the intrinsic base layer and adjacent the second E/C layer. The structure includes a gate structure on the intrinsic base layer and overhanging a lateral sidewall of the intrinsic base.

A semiconductor device, such as a heterojunction bipolar transistor (HBT), having a monocrystalline extrinsic base region may be formed via a method including steps of providing a substrate that includes a dielectric isolation region and a collector region that includes semiconductor material, forming a polycrystalline semiconductor layer over the substrate, forming a monocrystalline intrinsic base layer via epitaxial growth, where the intrinsic base layer is in direct contact with the polycrystalline semiconductor layer, removing the polycrystalline semiconductor layer after forming the monocrystalline intrinsic base layer, and forming a monocrystalline extrinsic base layer via epitaxial growth, where the monocrystalline extrinsic base layer is in direct contact with the monocrystalline intrinsic base layer.

A heterojunction bipolar transistor device includes a substrate, a metallic sub-collector layer, a collector layer, a base layer, an emitter layer, a base electrode, and a plurality of emitter strips. The metallic sub-collector layer is formed over the substrate. The collector layer is formed over the metallic sub-collector layer. The base layer is formed over the collector layer. The emitter layer is formed over the base layer. The base electrode is formed over the base layer and includes a plurality of base fingers. The plurality of emitter strips are formed over the emitter layer and are arranged alternately with the plurality of base fingers.

The present disclosure generally relates to semiconductor processing for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate and a bipolar junction transistor on the semiconductor substrate. The bipolar junction transistor includes a collector layer on the semiconductor substrate, a base layer on the collector layer, a raised base layer on the base layer, a dielectric spacer on the base layer and along a sidewall of the raised base layer, and an emitter layer on the base layer. The dielectric spacer is laterally between the raised base layer and the emitter layer. The emitter layer extends over the dielectric spacer and at least partially over the raised base layer. The raised base layer has a substantially continuous upper surface from a distance away from the emitter layer to the dielectric spacer underlying the emitter layer.

A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region an intrinsic base region, and a lateral base link region disposed between and in contact with each of the extrinsic base region and an intrinsic base region. The extrinsic base region, the lateral base link region, and a portion of the intrinsic base region each may be formed on a passivation layer disposed over an isolation region and a collector region of a substrate of the semiconductor device. The extrinsic base region and a first portion of the lateral base link region may be formed from polycrystalline semiconductor material. The intrinsic base region and a second portion of the lateral base link region may be formed from monocrystalline semiconductor material. The lateral base link region may be formed after formation of the extrinsic base region and the intrinsic base region.

In a semiconductor device, on a surface of a collector layer including a compound semiconductor of a first conductor type, facing in a first direction, a base layer including a compound semiconductor of a second conductor type opposite from the first conductor type is disposed. On a partial region of a surface of the base layer facing in the first direction, at least one emitter mesa including a compound semiconductor of the first conductor type and forming a heterojunction with the base layer is disposed. A collector electrode is on a surface of the collector layer facing in a second direction opposite to the first direction. An emitter electrode is on a surface of the emitter mesa facing in the first direction. A base electrode is on a region, in the surface of the base layer facing in the first direction, on which the emitter mesa is not disposed.

In a semiconductor device, on a surface of an emitter layer including a compound semiconductor of a first conductor type, facing in a first direction, a base layer including a compound semiconductor of a second conductor type opposite from the first conductor type and subjected to heterojunction to the emitter layer is disposed. At least one collector mesa including a compound semiconductor of the first conductor type is disposed on a surface of the base layer facing in the first direction. An emitter electrode is disposed on a surface of the emitter layer facing in a second direction opposite to the first direction. A base electrode continuously surrounding the collector mesa in plan view is disposed on the surface of the base layer facing in the first direction. A collector electrode is disposed on a surface of the collector mesa facing in the first direction.

The present disclosure generally relates to semiconductor processing for forming an emitter layer in a bipolar junction transistor (BJT). In an example, a BJT includes a collector, a base on the collector, and an emitter layer on the base. The emitter layer includes a first emitter sub-layer and a second emitter sub-layer over the first emitter sub-layer. The first emitter sub-layer includes boron and carbon. A concentration of carbon is uniform throughout the first emitter sub-layer. The second emitter sub-layer includes boron. A concentration of boron in the second emitter sub-layer is greater than a concentration of boron in the first emitter sub-layer.

A switching circuit forming a bidirectional switch between a first node and a second node and resting on a substrate includes a first branch with a first diode in series with a first heterojunction field-effect transistor, and a second branch with a second heterojunction field-effect transistor in series with a second diode, the first branch and the second branch being mounted in parallel to one another and so that the first diode and the second diode are arranged in antiparallel or in anti-series with respect to one another. The first transistor and the second transistor are each provided with a control gate facing a heterojunction band forming an active zone in which an electron gas is capable of being formed. The first diode is a Schottky diode with a metal electrode in contact with the heterojunction band, and the second diode is a Schottky diode with a metal electrode in contact with the heterojunction band. The first diode, the first transistor, the second diode, and the second transistor share the same active zone.