A method may include providing a device structure in the semiconductor device. The device structure may include a buried device contact, a first dielectric layer, disposed over the buried device contact; and a device element, where the device element includes a TiN layer. The method may include implanting an ion species into the TiN layer, wherein the ion species comprises a seed material for selective tungsten deposition.

An embodiment of the present disclosure provides a MIM capacitor by High-k dielectric and method for fabricating the same to prevent formation of oxygen-based interface films between a lower electrode and a dielectric layer, and between an upper electrode and a dielectric layer by stacking a first film formed of metal between the dielectric layer formed of a High-k material having a high dielectric constant and the lower electrode formed of metal, and a second film formed of metal between the dielectric layer and the upper electrode.

Two approaches for on-chip ESD detection include variable dielectric width capacitor, and vertical metal-oxide-semiconductor (MOS) capacitor MOSCAP array. The variable dielectric width capacitor approach employs metal plates terminated with sharp corners to enhance local electric field and facilitate ready breakdown of a thin dielectric between the metal plates. The vertical MOSCAP array is composed of a capacitor array connected in series. Both approaches are incorporated in an example 22 nm fully depleted silicon-on-insulator. Vertical MOSCAP arrays detect ESD events starting from about 6 V with about 6 V granularity, while the variable dielectric width capacitor is suitable for detection of high ESD voltage from about 40 V and above.

A semiconductor device includes a landing pad and a capacitor disposed on and electrically connected to the landing pad. The capacitor includes a cylindrical bottom electrode, a dielectric layer and a top electrode. The cylindrical bottom electrode is disposed on an in contact with the landing pads, wherein an inner surface the cylindrical bottom electrode includes a plurality of protruding portions, and an outer surface of the cylindrical bottom electrode includes a plurality of concaved portions. The dielectric layer is conformally disposed on the inner surface and the outer surface of the cylindrical bottom electrode, and covering the protruding portions and the concaved portions. The top electrode is conformally disposed on the dielectric layer over the inner surface and the outer surface of the cylindrical bottom electrode.

A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.

An inductor built-in substrate includes a core substrate having openings and first through holes, a magnetic resin filled in the openings and having second through holes, first through-hole conductors formed in the first through holes respectively such that each of the first through-hole conductors includes a metal film, and second through-hole conductors formed in the second through holes respectively such that each of the second through-hole conductors includes a metal film and that the metal film in each of the first through-hole conductors has a thickness that is greater than a thickness of the metal film in each of the second through-hole conductors.

A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.

A read-only memory cell array includes a first storage state memory cell and a second storage state memory cell. The first storage state memory cell includes a first transistor and a second transistor. The first transistor is connected to a source line and a word line. The second transistor is connected to the first transistor and a first bit line. The second storage state memory cell includes a third transistor and a fourth transistor. The third transistor is connected to the source line and the word line. The fourth transistor is connected to the third transistor and a second bit line. A gate terminal of the fourth transistor is connected to a gate terminal of the third transistor.

Various embodiments relate to an integrated circuit including a transistor device having input and output terminals, and an inductor-capacitor (LC) circuit coupled to one of the terminals of the transistor device. The LC circuit includes a capacitor having a top plate and a bottom plate, a inductor having a coil structure, and a connector configured to couple the inductor and an interior portion the top plate of the capacitor. The inductor at least partially overlaps the capacitor.

A resistance element includes a resistive film, in which the resistive film is adjacent to a protrusion formed on a surface of a semiconductor substrate, the protrusion including a step traversed by the resistive film.