Patent classifications
H04N5/347
IMAGING APPARATUS AND METHOD, AND IMAGE PROCESSING APPARATUS AND METHOD
The present technology relates to an imaging apparatus and method, and an image processing apparatus and method that make it possible to control the resolution of a detection image.
A resolution is set, and a restoration matrix is set including coefficients used when a restored image is restored from output pixel values of a plurality of pixel output units, of an imaging element including the plurality of pixel output units that receives incident light entering without passing through either an imaging lens or a pinhole, and each outputs one detection signal indicating an output pixel value modulated by an incident angle of the incident light, depending on the resolution set. The present disclosure can be applied to, for example, an imaging apparatus, an image processing apparatus, an information processing apparatus, an electronic device, a computer, a program, a storage medium, a system, and the like.
Hybrid output multiplexer for a high framerate CMOS imager
An imaging system is provided that includes a pixel array having a plurality of columns with rows of pixels and with each pixel having a plurality of photodiodes and a common readout circuit that stores respective accumulation voltages from each of the plurality of photodiodes. Moreover, the system includes row driver circuitry that control the pixel array for pixel addressing and readout, such that the respective accumulation voltages of the photodiodes is read out on a readout channel coupled to a bit line column, and a hybrid multiplexer that multiplexes and routes output signals from the pixel array to a video imaging device to be displayed thereon.
IMAGE SENSORS
The image sensor includes an array of photosensitive pixels comprising at least two sets of at least one pixel, control circuit configured to generate at least two different timing signals and adapted to control an acquisition of an incident optical signal by the pixels of the array, and distribution circuit configured to respectively distribute said at least two different timing signals in said at least two sets of at least one sensor, during the same acquisition of the incident optical signal.
Solid-state imaging device and electronic device
A solid-state imaging device including an imager that acquires image data, a processing unit that performs a process based on a neural network calculation model for data based on the image data acquired from the imager, and a control unit that switches between a first process mode of performing a first process at a first frame rate and, based on a result of the first process, a second process mode of performing a second process at a second frame rate.
Image sensing apparatus and image binning method thereof
Provided is an image sensing apparatus including an image sensor including a pixel array configured to output a raw image having a Bayer pattern, and an analog end configured to perform an analog binning process on groups of pixels of same colors included in same columns of each of a plurality of sub-kernels corresponding to a first green pixel, a red pixel, a blue pixel, and a second green pixel, and output median values for different colors, and a digital signal processor configured to perform a digital binning process on the median values for the different colors included in different columns of each of the plurality of sub-kernels, and output a binned image.
Pixel binning for hexa-deca RGBW color filter arrays
An image sensor includes a pixel array comprising a plurality of pixels, a color filter array comprising a plurality of color filter clusters overlying the pixel array, and readout circuitry configured to concurrently provide the pixels sharing the common filter cluster and having a first exposure time to a readout line for digital data conversion. Each of the color filter clusters includes a group of same color filters, and pixels sharing a common color filter cluster have different exposure times.
Luminance-adaptive processing of hexa-deca RGBW color filter arrays in CMOS image sensors
Techniques are described for luminance-adaptive processing of hexa-deca red-green-blue-white (RGBW) color filter arrays (CFAs) in digital imaging systems. Original image data is acquired by a sensor array configured according to a hexa-deca RGBW CFA pattern, and associated ambient luminance information is also acquired. The ambient luminance information is used to detect one of a number of predetermined luminance conditions. Based on the detected luminance condition, embodiments can determine whether and how much to downsample the original image data as part of the readout from the sensor array (e.g., using binning techniques), and whether and how much to remosaic and/or upsample the downsampled data to generate an RGB output array for communication to other processing components of the imaging system.
ELECTRONIC DEVICE INCLUDING IMAGE SENSOR HAVING MULTI-CROP FUNCTION
An electronic device includes first and second image sensors, an image signal processor, and a main processor. The first and second image sensors photograph an object in first and second FOVs to generate first and second signals, respectively. The image signal processor generates first image data based on the first signal, generates second image data based on the second signal, and generates cropped image data based on cropping ROI from the second image data. The main processor generates a first video stream based on the first image data, generates a second video stream based on the cropped image data, and outputs the first video stream to a display device. The main processor stops outputting the first video stream to the display device and initiates outputting the second video stream to the display device in response to receiving a user input command.
Solid-state imaging device, method of driving the same, and electronic apparatus
A solid-state imaging device includes a pixel array unit in which a plurality of imaging pixels configured to generate an image, and a plurality of phase difference detection pixels configured to perform phase difference detection are arranged, each of the plurality of phase difference detection pixels including a plurality of photoelectric conversion units, a plurality of floating diffusions configured to convert charges stored in the plurality of photoelectric conversion units into voltage, and a plurality of amplification transistors configured to amplify the converted voltage in the plurality of floating diffusions.
Imaging systems and methods for performing pixel binning and variable integration for analog domain regional feature extraction
Imaging circuitry may include circuits for implementing feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using variable charge integration times, variable resistors in the readout path, and/or variable switch on times in the readout path. The weighted pixels values may be binned and combined to obtain an output neuron voltage for at least one layer in a neural network. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories.