An imaging device with low power consumption is provided. The pixel of the imaging device includes first and second photoelectric conversion elements, and first to fifth transistors. A cathode of the first photoelectric conversion element is electrically connected to the first transistor. An anode of a second photoelectric conversion element is electrically connected to the second transistor. Imaging data of a reference frame is obtained using the first photoelectric conversion element, and then imaging data of a difference detection frame is obtained using the second photoelectric conversion element. After the imaging data of the difference detection frame is obtained, a first potential that is a potential of a signal output from the pixel and a second potential that is a reference potential are compared. Whether or not there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame is determined using the first potential and the second potential.

An image sensor operating in multiple resolution modes including a low resolution mode and a high resolution mode includes a pixel array including a plurality of pixels, wherein each pixel in the plurality of pixels comprises a micro-lens, a first subpixel including a first photodiode, a second subpixel including a second photodiode, and the first subpixel and the second subpixel are adjacently disposed and share a floating diffusion region. The image sensor also includes a row driver providing control signals to the pixel array to control performing of an auto focus (AF) function, such that performing the AF function includes performing the AF function according to pixel units in the high resolution mode and performing the AF function according to pixel group units in the low resolution mode. A resolution corresponding to the low resolution mode is equal to or less than ¼ times a resolution corresponding to the high resolution mode.

An imaging apparatus of the present disclosure includes: a pixel array in which a plurality of pixels including a first partial pixel, a second partial pixel, and a third partial pixel are arranged; and an addition processor that adds, for each of the pixels, a third partial pixel signal generated from the third partial pixel to either one of a first partial pixel signal generated from the first partial pixel and a second partial pixel signal generated from the second partial pixel, on the basis of a temperature of the pixel array.

Methods and apparatus to obtain exposure data for media exposure environment(s) are disclosed. An example apparatus disclosed herein includes processor circuitry to determine audience identification information and content identifying data.

Methods for capturing and transmitting images by an in-vivo device comprise operating a pixel array in a superpixel readout mode to capture probe image, for example, according to a time interval. Concurrently to capturing of each probe image, the probe image is evaluated alone or in conjunction with other probe image(s), and if it is determined that no event of interest is detected by the last probe image, or by the last few probe images, the pixel array is operated in the superpixel readout mode and a subsequent probe image is captured. However, if it is determined that the last probe image, or the last few probe images, detected an event of interest, the pixel array is operated in a single pixel readout mode and a single normal image, or a series of normal image, is captured and transmitted, for example, to an external receiver.

A first and second pixel units that perform FD addition are provided. The first pixel unit includes: a first switch transistor of which one source/drain electrode is connected to an FD; and a reset transistor that is connected between another source/drain electrode of the first switch transistor and a power supply node. The second pixel unit includes: a second switch transistor of which one source/drain electrode is connected to an FD; a third switch transistor of which one source/drain electrode is connected to another source/drain electrode of the second switch transistor; and a capacitive element that is connected between another source/drain electrode of the third switch transistor and a reference potential node. The respective other source/drain electrodes of the first switch transistor and the second switch transistor are electrically connected with each other.

The disclosure provides multimode configurable spectrometers, a method of operating a multimode configurable spectrometer, and an optical monitoring system. In one embodiment the multimode configurable spectrometer includes: (1) an optical sensor configured to receive an optical input and convert the optical input to electrical signals, wherein the optical sensor includes multiple active pixel regions for converting the optical input to the electrical signals, and (2) conversion circuitry, having multiple selectable converting circuits, that is configured to receive and convert the electrical signals to a digital output according to a selected one of the selectable converting circuits.

An image sensor, includes: a plurality of pixels arranged along a first direction, each of which includes a photoelectric conversion unit that generates an electric charge through photoelectric conversion of light, and outputs a signal generated based upon the electric charge generated in the photoelectric conversion unit; a first signal line to which signals from one or more pixels among the plurality of pixels are output; a second signal line to which a signal from another pixel among the plurality of pixels is output; and an arithmetic unit that executes an arithmetic operation with a signal generated by combining the signals from the one or more pixels output to the first signal line and the signal output to the second signal line.

A solid-state imaging device includes an imager configured to acquire image data, a processing unit configured to perform a process based on a neural network calculation model for data based on the image data acquired from the imager, and a control unit configured to switch between a first process mode of performing a first process at a first frame rate and, based on a result of the first process, a second process mode of performing a second process at a second frame rate.

Embodiments relate to image signal processors (ISP) that include binner circuits that down-sample an input image. An input image may include a plurality of pixels. The output image of the binner circuit may include a reduced number of pixels. The binner circuit may include a plurality of different operation modes. In a bin mode, the binner circuit may blend a subset of input pixel values to generate an output pixel quad. In a skip mode, the binner circuit may select one of the input pixel values as the output pixel. The selection may be performed randomly to avoid aliasing. In a luminance mode, the binner circuit may take a weighted average of a subset of pixel values having different colors. In a color value mode, the binner circuit may select one of the colors in a subset of pixel values as an output pixel value.