A solid-state imaging device (10) includes an imager (11) configured to acquire image data, a processing unit (14) configured to perform a process based on a neural network calculation model for data based on the image data acquired from the imager, and a control unit (12) configured to switch between a first process mode of performing a first process at a first frame rate and, based on a result of the first process, a second process mode of performing a second process at a second frame rate.

A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.

One embodiment of an apparatus includes a reference position receiving unit configured to receive intermediate or end panorama reference position information input by a user, and a control unit configured to control an imaging device to begin generating a plurality of images to be used to generate a panoramic image based on the intermediate or end panorama reference position information input by the user after the reference position receiving unit receives the intermediate or end panorama reference position information.

A solid-state image pickup device includes: comparators; counters; and a control portion for carrying out control in such a way that in a phase of an addition mode, the two comparators and the two counters corresponding to the two pixel columns, respectively, are set as a unit, 1 is added to a second digit of one counter of the two counters when both the comparison results from the two comparators has a first logic, 1 is added to a first digit of the one counter when one of the comparison results from the two comparators has the first logic, and 1 is added to none of the first digit and the second digit of the one counter when both the comparison results from the two comparators has a second logic.

A solid state imaging device includes: a pixel array unit that has a plurality of pixels 2-dimensionally arranged in a matrix and a plurality of signal lines arranged along a column direction; A/D conversion units that are provided corresponding to the respective signal lines and convert an analog signal output from a pixel through the signal line into a digital signal; and a switching unit that switches or converts the analog signal output through each signal line into a digital signal using any of an A/D conversion unit provided corresponding to the signal line through which the analog signal is transmitted, and an A/D conversion unit provided corresponding to a signal line other than the signal line through which the analog signal is transmitted.

A solid state imaging device includes: a pixel array unit that has a plurality of pixels 2-dimensionally arranged in a matrix and a plurality of signal lines arranged along a column direction; A/D conversion units that are provided corresponding to the respective signal lines and convert an analog signal output from a pixel through the signal line into a digital signal; and a switching unit that switches or converts the analog signal output through each signal line into a digital signal using any of an A/D conversion unit provided corresponding to the signal line through which the analog signal is transmitted, and an A/D conversion unit provided corresponding to a signal line other than the signal line through which the analog signal is transmitted.

Disclosed is an image sensor. The image sensor includes an active pixel sensor array including first to fourth pixel units sequentially arranged in a column direction, and each of the first to fourth pixel units is composed of a plurality of pixels. A first pixel group including the first and second pixel units is connected to a first column line, and a second pixel group including the third pixel unit and the fourth pixel unit is connected to a second column line. The image sensor includes a correlated double sampling circuit including first and second correlated double samplers and configured to convert a first sense voltage sensed from a selected pixel of the first pixel group and a second sense voltage sensed from a selected pixel of the second pixel group into a first correlated double sampling signal and a second correlated double sampling signal, respectively.

An electronic device according to various embodiments of the present invention comprises an image sensor and a processor, wherein the image sensor comprises a microlens and a light-receiving sensor pixel capable of converting light having passed through the microlens into an electrical signal, the light-receiving sensor pixel comprises a first floating diffusion area and a second floating diffusion area, the light-receiving sensor pixel is set, as a first area and a second area having different sizes, in accordance with the activation of either the first floating diffusion area or the second floating diffusion area, a signal generated by the light-receiving sensor pixel can be classified and read out as a first signal corresponding to the first area and a second signal corresponding to the second area, and the processor can be set so as to: use the image sensor so as to activate the first floating diffusion area, thereby acquiring a first image of an external object; use the image sensor so as to activate the second floating diffusion area, thereby acquiring a second image of the external object; and synthesize at least a portion of the first image and at least a portion of the second image, thereby generating a third image having a resolution higher than that of the first or second image. Additional various embodiments are possible.

An imaging apparatus and electronic equipment configured for reduced power consumption are disclosed. In one example, an imaging apparatus includes a pixel array unit including a first pixel portion and a second pixel portion different from the first pixel portion. Each of the first pixel portion and the second pixel portion includes a first photoelectric conversion unit and a second photoelectric conversion unit adjacent to the first photoelectric conversion unit. The pixel array unit includes a first drive line connected to the first photoelectric conversion unit of the first pixel portion and the second pixel portion, a second drive line connected to the second photoelectric conversion unit of the first pixel portion, and a third drive line connected to the second photoelectric conversion unit of the second pixel portion. The t technology can, for example, be applied in a CMOS image sensor having pixels for phase difference detection.

An RGBW image sensor, a binning method in an image sensor, and a computer readable medium for performing the method are provided, and the binning method in an image sensor includes selecting one or more binning target pixels for each of a red pixel, a green pixel, a blue pixel, and a white pixel, constituting a pixel array of an RGBW image sensor with a uniform array pattern, generating binning pixel data for each of the red pixel, the green pixel, the blue pixel, and the white pixel, based on pieces of pixel data corresponding to the binning target pixel, and rearranging pixels, represented by the binning pixel data, to be equal to the entirety or a portion of the uniform array pattern and to be equally spaced apart from each other.