A flicker detection circuit is provided. The flicker detection circuit may include a flicker detection correlated double sampling (FD CDS) circuit including first to sixth switches turned on or off based on a control signal, and first to fourth capacitors, the FD CDS circuit being configured to receive a flicker pixel signal output from at least one pixel, summate with an output offset signal, and amplify the summation based on a gain to form a flicker detection signal; and an analog-to-digital converter (ADC) configured to quantize the flicker detection signal.

Disclosed is an image sensing device including a current supply circuit coupled between a supply terminal of a first voltage and a pair of output terminals, an input circuit coupled between the pair of output terminals and a common node, and suitable for receiving a pixel signal and a ramp signal, and a mirroring circuit coupled between the common node and a supply terminal of a second voltage, and suitable for compensating for an operating current, which flows between the common node and the supply terminal of the second voltage, based on a reference current when generating the operating current by mirroring the reference current.

There is provided a semiconductor device that can minimize deterioration of performance of a capacitor due to a bonding process. Between a first substrate and a second substrate bonded to each other, the semiconductor device includes a first electrode which is provided in the first substrate and of which one surface is positioned on the same surface as a bonding surface between the first substrate and the second substrate, and a second electrode which is provided in the second substrate and of which one surface is positioned on the same surface as a bonding surface and bonded to one surface of the first electrode. Therefore, the semiconductor device includes at least one of a first capacitor which is provided in the first substrate and of which one electrode is electrically connected to a non-exposed surface of the first electrode and a second capacitor which is provided in the second substrate and of which one electrode is electrically connected to a non-exposed surface of the second electrode.

To provide an imaging device that allows miniaturization to be achieved in an in-plane direction without impairing operation performance. This imaging device includes a first pixel and a second pixel. The first pixel includes m (m represents an integer greater than or equal to 2) first wiring lines and m first gate electrodes that are coupled to the m respective first wiring lines. The second pixel includes n (n represents a natural number smaller than m) second wiring lines and n second gate electrodes that are coupled to the n respective second wiring lines.

A solid-state imaging device includes: pixels disposed in a matrix of pixel rows and pixel columns; control wires provided for the pixel rows or the pixel columns, and each connected to at least two pixels out of the pixels, the at least two pixels being included in one of the pixel rows or the pixel columns for which the control wire is provided; drive circuits that are provided for the control wires, each include buffer elements in at least two stages, and each output a control signal to one of the control wires for which the drive circuit is provided, the buffer elements in the at least two stages being connected in series; and a first wire that short-circuits output wires of the buffer elements in one of the at least two stages in at least two of the plurality of drive circuits.

Provided are a solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus capable of reading signals produced with different conversion gains and having different signal directions.

A pixel signal processing part 400 includes a first reading part 410 and a second reading part 420. Of a pixel signal PIXOUT input into an input node ND401, the first reading part 410 inverts the signal direction of a first-conversion-gain signal (HCGRST, HCGSIG) and outputs an inverted first-conversion-gain signal (HCGRST, HCGSIG), which has been subjected to inversion and amplification, to an AD converting part 430 via a connection node ND402. Of the pixel signal PIXOUT input into the input node ND401, the second reading part 420 keeps the signal direction of a second-conversion-gain signal (LCGSIG, LCGRST) unchanged, and outputs a non-inverted second-conversion-gain signal (LCGSIG, LCGRST) to the AD converting part 430 via the connection node ND402.

An image sensing device includes a photoelectric element configured to generate an electric charge in response to light; first and second floating diffusions configured to store the electric charge; a transfer gate having a first end connected to the photoelectric element and a second end connected to the first floating diffusion; a reset transistor configured to reset voltages of the first and second floating diffusions based on a reset signal; a first dual conversion gain (DCG) transistor having a first end connected to the first floating diffusion and a second end connected to the second floating diffusion; first and second pixel circuits configured to generate first and second output voltages based on the first and second floating diffusions; and first and second analog to digital converters configured to receive the first and second output voltages and convert them to first and second digital signals.

A technique capable of improving linearity at a low illuminance is provided. A solid-state sensing image device includes: a pixel array including a plurality pixels arranged in a matrix form and a plurality of pixel signal lines connected to the plurality of pixels and receiving pixel signals supplied from the plurality pixels; a column-parallel A/D converting circuit connected to the plurality of pixel signal lines; and a reference-voltage generating circuit generating ramp-wave reference voltage that linearly changes in accordance with time passage. The column-parallel A/D converting circuit includes a first A/D converter, the first A/D converter includes: a first input terminal connected to the pixel signal line; a second input terminal receiving the reference voltage; and an offset generating circuit connected to the first input terminal and generating an offset voltage for the first input terminal.

In an imaging device, a photoelectric converter of a first pixel and a photoelectric converter of a second pixel are arranged along a first direction. At least part of a charge accumulation portion of the first pixel is disposed between the photoelectric converter of the first pixel and the photoelectric converter of the second pixel. An exit surface of a light guiding path of the first pixel is longer in a second direction orthogonal to the first direction in plan view than in the first direction.

An image sensor includes a pixel array including first pixels and second pixels, each of the first and second pixels including photodiodes, a sampling circuit detecting a reset voltage and a pixel voltage from the first and second pixels and generating an analog signal, an analog-to-digital converter image data from the analog signal, and a signal processing circuit generating an image using the image data. Each of the first pixels includes a first conductivity-type well separating the photodiodes and having impurities of a first conductivity-type. The photodiodes have impurities of a second conductivity-type different from the first conductivity-type. Each of the second pixels includes a second conductivity-type well separating the photodiodes and having impurities of the second conductivity-type different from the first conductivity-type. A potential level of the second conductivity-type well is higher than a potential level of the first conductivity-type well.