One embodiment of the disclosure relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.

A semiconductor device include a substrate, a first well region formed in the substrate, a first isolation structure formed in the first well region, a Schottky barrier structure formed on the first well region, and a plurality of assist structures formed on the first well region. The substrate includes a first conductivity type, the first well region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The assist structures physically contact the first well region.

A semiconductor device include a substrate, a first well region formed in the substrate, a first isolation structure formed in the first well region, a Schottky barrier structure formed on the first well region, and a plurality of assist structures formed on the first well region. The substrate includes a first conductivity type, the first well region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The assist structures physically contact the first well region.

This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

A semiconductor device including an insulating film in a first region of a semiconductor substrate; a first impurity region and a second impurity region of a first conductivity type, each of the regions including a part located deeper than the insulating film in contact with each other, and the insulating film being sandwiched by the first and second impurity regions in planar view in the first region of the semiconductor substrate; a metal silicide film on the first impurity region and in Schottky junction with the first impurity region; a first impurity of the first impurity region having a peak of a concentration profile deeper than a bottom of the insulating film; a second impurity of the second impurity region having a concentration higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film.

A semiconductor device includes a plurality of drift regions of a plurality of field effect transistor structures arranged in a semiconductor substrate. The plurality of drift regions has a first conductivity type. The semiconductor device further includes a plurality of compensation regions arranged in the semiconductor substrate. The plurality of compensation regions has a second conductivity type. Each drift region of the plurality of drift regions is arranged adjacent to at least one compensation region of the plurality of compensation regions. The semiconductor device further includes a Schottky diode structure or metal-insulation-semiconductor gated diode structure arranged at the semiconductor substrate.

A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the termination trench by the liner oxide layer having a second thickness. In one embodiment, the second thickness is greater than the first thickness. In another embodiment, the trench gate in each of the active trench and the termination trench is formed as a single polysilicon layer.

[Problem] To provide a semiconductor device capable of suppressing a channel current without increasing manufacturing processes, and capable of accurately forming a channel current suppression structure. [Solution] A semiconductor device 1 according to the present invention includes: a substrate 10; an epitaxial layer 20 formed on the substrate 10; and an insulating film 35 provided on one surface 20a side of the epitaxial layer 20. An active portion 40 provided with a predetermined element and a channel current suppression portion 50 being at a termination portion 70 side and provided outside the active portion 40 are provided on the one surface 20a side of the epitaxial layer 20 via the insulating layer 35. The channel current suppression portion 50 is provided with a trench 51 for suppressing the channel current flowing from the active portion 40 to the termination portion 70.

A diode device and manufacturing method thereof are provided. The diode device includes a substrate, an epitaxial layer, a trench gate structure, a Schottky diode structure and a termination structure. An active region and a termination region are defined in the epitaxial layer. The Schottky diode structure and the trench gate structure are located in the active region and the termination structure is located in the termination region. The termination structure includes a termination trench formed in the epitaxial layer, a termination insulating layer, a first spacer, a second spacer and a first doped region. The termination insulating layer is conformingly formed on inner walls of the termination trench. The first and second spacers are disposed on two sidewalls of the termination trench. The first doped region formed beneath the termination trench has a conductive type reverse to that of the epitaxial layer.

A semiconductor device comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; an insulating portion provided on the first semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region and having a hicher carrier concentration of the second conductivity type than that of the second semiconductor region; and a first electrode provided on the insulating portion and the third semiconductor region, the first electrode having a portion which is aligned with the second semiconductor region in a second direction perpendicular to a first direction being from the first semiconductor region to the second semiconductor region, and the first electrode being in contact with the second semiconductor region and the third semiconductor region.