The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.

One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and tantalum nitride terminated through wafer via. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. A metal layer in the tantalum nitride terminated through wafer via is included in an electrical connection between the power amplifier on a front side of a substrate and a conductive layer on a back side of the substrate. Other embodiments of the module are provided along with related methods and components thereof.

An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.

Provided are a power device having an improved field stop layer and a method of manufacturing the same. The method can include performing a first ion implant process by implanting impurity ions of a first conductive type into a front surface of a semiconductor substrate to form an implanted field stop layer where the semiconductor substrate is the first conductive type. The method can include performing a second ion implant process by implanting impurity ions of the first conductive type into a first part of the implanted field stop layer such that an impurity concentration of the first part of the implanted field stop layer is higher than an impurity concentration of a second part of the implanted field stop layer.

The present application teaches, inter alia, methods and circuits for operating a B-TRAN (double-base bidirectional bipolar junction transistor). Exemplary base drive circuits provide high-impedance drive to the base contact region on the side of the device instantaneously operating as the collector. (The B TRAN is controlled by applied voltage rather than applied current.) Current signals operate preferred implementations of drive circuits to provide diode-mode turn-on and pre-turnoff operation, as well as a hard ON state with low voltage drop (the transistor-ON state). In some preferred embodiments, self-synchronizing rectifier circuits provide adjustable low voltage for gate drive circuits. In some preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while base current at that terminal is monitored, so no more base current than necessary is applied. This solves the difficult challenge of optimizing base drive in a B-TRAN.

A symmetrically-bidirectional bipolar transistor circuit where the two base contact regions are clamped, through a low-voltage diode and a resistive element, to avoid bringing either emitter junction to forward bias. This avoids bipolar gain in the off state, and thereby avoids reduction of the withstand voltage due to bipolar gain.

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

A method of making a bipolar transistor includes forming an extrinsic base layer over an oxide layer on a substrate. After an emitter window is opened in the extrinsic base layer, a sidewall spacer is formed on the sidewall of the emitter window. After forming the sidewall spacer, the oxide layer may be etched away to expose the substrate and to form a cavity extending beneath the extrinsic base layer. Subsequently, a monocrystalline emitter is formed in the emitter window whereby a peripheral part of the monocrystalline emitter fills the cavity. An anneal is then performed to form an emitter diffusion region and a base link region of the bipolar transistor.

An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor that is capable of reducing a base resistance and a turn-on voltage as compared to a conventional technique are provided. In an epitaxial wafer for a heterojunction bipolar transistor that includes a collector layer made of GaAs, a base layer (second base layer) formed on the collector layer and made of InGaAs, and an emitter layer formed on the second base layer and made of InGaP, a base layer (first base layer) made of GaAs is interposed between the collector layer and the second base layer.