According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon.

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Provided is a semiconductor device including: a front surface electrode provided above the semiconductor substrate; a trench contact portion at which the front surface electrode and the mesa portion are connected to each other in the transistor portion; and a front surface contact portion at which the front surface electrode and the mesa portion are connected to each other in the diode portion, where a lower end of the front surface contact portion is arranged above a lower end of the trench contact portion.

Methods of manufacture of advanced electronic and photonic structures including heterojunction transistors, transistor lasers and solar cells and their related structures, are described herein. Other embodiments are also disclosed herein.

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

One aspect of this disclosure is a power amplifier module that includes a power amplifier; a wire bond pad electrically connected to the power amplifier, the wire bond pad including a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer; and a conductive trace having a top surface with a plated portion and an unplated portion surrounding the plated portion, the wire bond pad being disposed over the plated portion. Other embodiments of the module are provided along with related methods and components thereof.

The present application teaches, inter alia, methods and circuits for operating B-TRANs (double-base bidirectional bipolar junction transistors). Base drive circuits provide high-impedance drive to the base contact region on whichever side of the device is (instantaneously) operating as the collector. (B-TRANs, unlike other bipolar junction transistors, are controlled by applied voltage, not applied current.) Control signals operate preferred drive circuits, providing diode-mode turn-on and pre-turnoff operation, and a hard ON state with a low voltage drop (the transistor-ON state). In some (not necessarily all) preferred embodiments, a self-synchronizing rectifier circuit provides an adjustable low voltage for the gate drive circuit. Also, in some preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while monitoring the base current at that terminal, so that no more base current than necessary is applied. This solves the difficult challenge of optimizing base drive in B-TRANs.

The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

A semiconductor device includes: a drift layer; a mesa region that is interposed between adjacent trenches on the drift layer; a gate electrode buried in each trench through a gate insulating film; a base region of buried in the mesa region; a plurality of emitter regions that are periodically buried in a surface layer portion of the base region along a longer direction of the trench; and contact regions that are alternately buried in the longer direction together with the emitter regions such that each emitter region is interposed between the contact regions, are deeper than the emitter region, and extend immediately below the emitter region so as to be separated from each other, a contact-region contact-width in the longer direction defined in a surface of the contact region being less than an emitter-region contact-width in the longer direction defined in a surface of the emitter region.