The present application relates to a turn-off power semiconductor device having a wafer with an active region and a termination region surrounding the active region, a rubber ring as an edge passivation for the wafer and a gate ring placed on a ring-shaped gate contact on the termination region for contacting the gate electrodes of a thyristor cell formed in the active region of the wafer. In the turn-off power semiconductor device, the outer circumferential surface of the gate ring is in contact with the rubber ring to define the inner border of the rubber ring. The area consumed by the ring-shaped gate contact on the termination or edge region can be minimized. The upper surface of the gate ring and the upper surface of the rubber ring form a continuous surface extending in a plane parallel to the first main side of the wafer.

A RC power semiconductor is provided which comprises a plurality of diode cells and a plurality of GCT cells. Each GCT cell comprises a first cathode layer with at least three cathode layer regions, which are separated from each other by a base layer. In orthogonal projection onto a plane parallel to the first main side each one of the cathode layer regions is strip-shaped and a width (w, w), wherein the diode cells alternate with the GCT cells in a lateral direction in at least a mixed part, wherein in each GCT cell, the width (w) of each one of the two outer cathode layer regions next to a diode cell neighboring to that GCT cell is less than the width (w) of any intermediate cathode layer region between the two outer cathode layer regions in that GCT cell.

The present disclosure provides a semiconductor device, including a substrate, a first active region in the substrate, a second active region in the substrate and adjacent to the first active region, an isolation region in the substrate and between the first active region and the second active region, and a dummy gate overlapping with the isolation region, wherein an entire bottom width of the dummy gate is greater than an entire top width of the isolation region.

A display apparatus may include a first inorganic insulating layer disposed between a first semiconductor layer and a first gate electrode, a second inorganic insulating layer disposed between the first gate electrode and a capacitor electrode, a third inorganic insulating layer disposed on the capacitor electrode, a fourth inorganic insulating layer disposed between a second semiconductor layer and a second gate electrode, a fifth inorganic insulating layer disposed on the second gate electrode, a 1st-1 connection electrode disposed over the fifth inorganic insulating layer and electrically connected to the first semiconductor layer through a 1st-1 contact hole passing through the first to the fifth inorganic insulating layer, and a 1st-1 bridge contact layer covering a portion of the fifth inorganic insulating layer, an inner surface of the 1st-1 contact hole, and a portion of the first semiconductor layer corresponding to the 1st-1 contact hole.

A display apparatus may include a first inorganic insulating layer disposed between a first semiconductor layer and a first gate electrode, a second inorganic insulating layer disposed between the first gate electrode and a capacitor electrode, a third inorganic insulating layer disposed on the capacitor electrode, a fourth inorganic insulating layer disposed between a second semiconductor layer and a second gate electrode, a fifth inorganic insulating layer disposed on the second gate electrode, a 1st-1 connection electrode disposed over the fifth inorganic insulating layer and electrically connected to the first semiconductor layer through a 1st-1 contact hole passing through the first to the fifth inorganic insulating layer, and a 1st-1 bridge contact layer covering a portion of the fifth inorganic insulating layer, an inner surface of the 1st-1 contact hole, and a portion of the first semiconductor layer corresponding to the 1st-1 contact hole.