A method for manufacturing a SiC semiconductor device includes the steps of: forming an impurity region in a SiC layer; forming a first carbon layer on a surface of the SiC layer having the impurity region formed therein, by selectively removing silicon from the surface; forming a second carbon layer on the first carbon layer; and heating the SiC layer having the first carbon layer and the second carbon layer formed therein.

A semiconductor device includes a first load terminal at a first surface of a semiconductor body and a second load terminal at the opposing surface. An active device area is surrounded by an edge termination area. Load terminal contacts are absent in the edge termination area and are electrically connected to the semiconductor body in the active device area at the first surface. A positive temperature coefficient structure is between at least one of the first and second load terminals and a corresponding one of the first and second surfaces. Above a maximum operation temperature specified for the semiconductor device, a specific resistance of the positive temperature coefficient structure increases by at least two orders of magnitude within a temperature range of at most 50 K. A degree of area coverage of the positive temperature coefficient structure is greater in the edge termination area than in the active device area.

A recess where an edge termination region is lower than an active region is disposed on a silicon carbide base body and an n.sup.-type silicon carbide layer is exposed at a bottom of the recess. In the portion of the n.sup.-type silicon carbide layer exposed at the bottom of the recess, first and second JTE regions configuring a JTE structure are disposed. The first JTE region is disposed from the bottom of the recess, along a side wall and covers a bottom corner portion of the recess. The first JTE region overlaps an outermost first p-type base region at the bottom corner portion. The first JTE region has an impurity concentration that is highest at the portion overlapping the first p-type base region and distribution of the impurity concentration in a depth direction peaks at a portion deeper than the bottom of the recess.

It is an objective to improve reverse surge withstand capability of a semiconductor device, for example, a Schottky barrier diode. A p-type semiconductor section 14 includes a p+ type semiconductor portion (first concentration portion) 14a and a p type semiconductor portion (second concentration portion) 14b, which have different impurity concentrations from each other. Additionally, a part of a side surface 13S of a metal portion 13 and a part of a bottom surface 13B of the metal portion 13 connected to the side surface 13S thereof are in contact with a part of the p+ type semiconductor portion 14a. Further, at least a part of a side surface 14bS of the p type semiconductor portion 14b is in contact with a side surface 14aS of the p+ type semiconductor portion 14a.

A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region having a second conductivity type, a first insulating layer on the first and second semiconductor regions, and field plate electrodes are provided in the first insulating layer at different distances from the first semiconductor layer. A first field plate electrode is at a first distance, a second field plate electrode is at a second distance greater than the first distance, and a third field plate electrode is at a distance greater than the second distance. The first through third field plate electrodes are electrically connected to each other and the third electrode is electrically connected to the second semiconductor region.

A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.

In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.

An electronic device is integrated on a chip of semiconductor material having a main surface and a substrate region with a first type of conductivity. The electronic device has a vertical MOS transistor, formed in an active area having a body region with a second conductivity type. A set of one or more cells each one having a source region of the first conductivity, a gate region of electrically conductive material in a gate trench extending from the main surface in the body region and in the substrate region, and an insulating gate layer, and a termination structure with a plurality of termination rings surrounding at least part of the active area on the main surface, each termination ring having a floating element of electrically insulating material in the termination trench extending from the main surface in the chip and at least one bottom region of said semiconductor material of the second conductivity type extending from at least one deepest portion of a surface of the termination trench in the chip; the termination trenches have a depth from the main surface decreasing moving away from the active area.

A method for manufacturing a silicon carbide semiconductor device includes steps of preparing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, forming a groove portion in the first main surface of the silicon carbide substrate, and cutting the silicon carbide substrate at the groove portion. The step of forming the groove portion includes a step of thermally etching the silicon carbide substrate using chlorine. Thereby, a method for manufacturing a silicon carbide semiconductor device capable of suppressing damage to a chip is provided.