The present disclosure relates to a power module that has a housing with an interior chamber and a plurality of switch modules interconnected to facilitate switching power to a load. Each of the plurality of switch modules comprises at least one transistor and at least one diode mounted within the interior chamber and both the at least one transistor and the at least one diode are majority carrier devices, are formed of a wide bandgap material system, or both. The switching modules may be arranged in virtually any fashion depending on the application. For example, the switching modules may be arranged in a six-pack, full H-bridge, half H-bridge, single switch or the like.

An IGBT includes an emitter electrode, base regions, an emitter region, a collector region, a collector electrode, a gate insulating film provided in contact with the silicon carbide semiconductor region, the emitter region, and the base region, and a gate electrode that faces the gate insulating film. A FWD includes a base contact region provided adjacent to the emitter region and electrically connected to the emitter electrode, and a cathode region disposed in the upper layer part on the other main surface side of the silicon carbide semiconductor region, provided adjacent to the collector region, and electrically connected to the collector electrode. The IGBT further includes a reduced carrier-trap region disposed in a principal current-carrying region of the silicon carbide semiconductor region located above the collector region and having a smaller number of carrier traps than the silicon carbide semiconductor region located above the cathode region.

A method of manufacturing a semiconductor device includes forming a cavity in a first semiconductor layer formed on a semiconducting base layer, the cavity extending from a process surface of the first semiconductor layer at least down to the base layer, forming a recessed mask liner on a portion of a sidewall of the cavity distant to the process surface or a mask plug in a portion of the cavity distant to the process surface, and growing a second semiconductor layer on the process surface by epitaxy, the second semiconductor layer spanning the cavity.

In one general aspect, a method of fabricating a power device can include preparing a semiconductor substrate of a first conductivity type, and forming a first Field Stop (FS) layer and a second FS layer.

A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface of the semiconductor body. The reservoir region includes no superjunction structure or a second superjunction structure with a mean second vertical extension smaller than the first vertical extension.

A method for manufacturing a semiconductor device is provided. The method includes forming a first semiconductor element and a second semiconductor element in a semiconductor wafer. The first semiconductor element includes a first electrode formed on a front surface of the semiconductor wafer. The second semiconductor element is adjacent to the first semiconductor element and includes a second electrode formed on the front surface. The method further includes forming a first insulating layer on the front surface located at a first boundary portion between the first electrode and the second electrode; applying a specific potential different from a potential of the second electrode on the first electrode after the formation of the first insulating layer; and cutting the semiconductor wafer at the first boundary portion so as to divide the first semiconductor element from the second semiconductor element.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.

An IGBT device and a method for packaging a whole-wafer IGBT chip. The IGBT device comprises: an entire wafer IGBT chip, the upper surface thereof comprising a central gate connection zone and a plurality of emitter connection zones surrounding the central gate connection zone, and the lower surface thereof comprising a collecting zone, wherein the emitter connection zones located on the surface of a failure cellular zone of the chip are thinned; a collector washer which is fixed on the lower surface of the chip, and an emitter washer which is fixed on the upper surface of the chip; a collector electrode which is electrically contacted with the collector washer, and an emitter electrode which is electrically contacted with the emitter washer; and a gate leading wire which is connected to the central gate connection zone.

A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n.sup.+-type emitter region, a p-type base region, and an n.sup.-type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p.sup.+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n.sup.-type drift region, a plurality of emitter trenches formed between the plurality of gate trenches adjacent to each other, a buried electrode filled via an insulating film in the plurality of emitter trenches, and electrically connected with the n.sup.+-type emitter region, and a p-type floating region formed between the plurality of emitter trenches, and the p-type floating region is formed deeper than the p-type base region, and includes an overlap portion that goes around to a lower side of an emitter trench closest to the gate trench out of the plurality of emitter trenches and has an end portion positioned on a side closer to the gate trench with respect to a center in a width direction of the emitter trench.

To provide a semiconductor device in which an edge termination structure can be made smaller easily. A semiconductor device is provided, the semiconductor device including an active region and an edge termination structure formed on a front surface side of a semiconductor substrate, wherein an edge termination structure has a guard ring provided surrounding an active region on a front surface side of a semiconductor substrate, a first field plate provided on a front surface side of a guard ring, an electrode unit provided on a front surface side of a first field plate, a second field plate provided between a first field plate and a electrode unit, and a conductive connecting unit which mutually electrically connects a first field plate, an electrode unit, a second field plate, and a guard ring.