A switching loss is prevented from being deteriorated by suppressing increase in a gate capacitance due to a cell shrink of an IE type trench gate IGBT. A cell formation region is configured of a linear active cell region, a linear hole collector cell region, and a linear inactive cell region between them. Then, upper surfaces of the third and fourth linear trench gate electrodes which are formed so as to sandwich both sides of the linear hole collector cell region and electrically connected to an emitter electrode are positioned to be lower than upper surfaces of the first and second linear trench gate electrodes which are formed so as to sandwich both sides of the linear active cell region and electrically connected to a gate electrode.

A diffusion diode including a p.sup.+ diffusion region, a p-type diffusion region, and an n.sup.+ diffusion region is formed in the front surface of a semiconductor substrate. A polysilicon diode including a p.sup.+ layer and an n.sup.+ layer is formed on top of a local insulating film formed on the front surface of the semiconductor substrate and faces the diffusion diode in the depth direction. The diffusion diode and the polysilicon diode are reverse-connected by electrically connecting the n.sup.+ diffusion region to the n.sup.+ layer, thereby forming a lateral protection device. The p.sup.+ layer and p.sup.+ diffusion region are respectively electrically connected to a high voltage first terminal and a low voltage second terminal of the lateral protection device. The polysilicon diode blocks a forward current generated in the diffusion diode when the electric potential of the first terminal becomes lower than the electric potential of the second terminal.

The power module includes: a ceramics substrate; a source electrode pattern, a drain electrode pattern, a source signal electrode pattern, and a gate signal electrode pattern respectively disposed on the ceramics substrate; a semiconductor device disposed on the drain electrode pattern, the semiconductor device comprising a source pad electrode and a gate pad electrode at a front surface side; a divided leadframe for source bonded to the source electrode pattern and the source pad electrode; and a divided leadframe for gate pad electrode bonded to a gate pad electrode. There is provided a power module having a simplified structure, fabricated through a simplified process, and capable of conducting a large current; and a fabrication method for such a power module.

Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.

A silicon carbide semiconductor device includes a silicon carbide substrate, a gate electrode, and a drain electrode. A trench is formed in a second main surface of the silicon carbide substrate. The silicon carbide substrate includes a first conductivity type region, a body region, a source region, and a first second conductivity type region surrounded by the first conductivity type region. The trench is formed of a side wall surface and a bottom portion. An impurity concentration of the first second conductivity type region is lower than an impurity concentration of the first conductivity type region. The first second conductivity type region is provided so as to face a region between a first contact point and a second contact point and be separated apart from a first main surface.

Provided is a semiconductor device comprising: a first conductivity type base layer having a MOS gate structure formed on its front surface side; a second conductivity type first collector layer formed on a rear surface side of the base layer; a second conductivity type second collector layer formed on a rear surface side of the first collector layer with a material the same with that of the base layer, the second collector layer formed to be thinner than the first collector layer and having a higher impurity concentration than that of the first collector layer; a collector electrode formed on a rear surface side of the second collector layer; and a second conductivity type separation layer surrounding the MOS gate structure on a front surface side of the base layer and formed from a front surface of the base layer to a front surface of the first collector layer.

A MOS semiconductor device has a MOS structure, including a p.sup. region that surrounds an n.sup.+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n.sup.+-type source region and a surface layer of an n.sup. layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.

A semiconductor device is provided with a first well region of a first conduction type having a first voltage (voltage VB) applied thereto, a second well region of a second conduction type formed in the surface layer section of the first well region and having a second voltage (voltage VS) different from the first voltage applied thereto, and a charge extracting region of the first conduction type formed in the surface layer section of the second well region and having the first voltage applied thereto. This inhibits the operation of a parasitic bipolar transistor.

Disclosed is a method for removing a polysilicon protection layer (12) on a back face of an IGBT having a field stop structure (10). The method comprises thermally oxidizing the polysilicon protection layer (12) on the back face of the IGBT until the oxidation is terminated on a gate oxide layer (11) located above the polysilicon protection layer (12) to form a silicon dioxide layer (13), and removing the formed silicon dioxide layer (13) and the gate oxide layer (11) by a dry etching process. The method for removing the protection layer is easier to control.

Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.