According to one embodiment, a semiconductor memory device includes a substrate, a first insulating film, a stacked body, and a first pillar. At least a portion of an upper layer portion of the substrate is conductive. The first insulating film is provided in a portion of the substrate. The stacked body includes conductive films and insulating films stacked alternately in a first direction. The conductive films and the insulating films are provided on the substrate and on the first insulating film. The first pillar pierces the stacked body in the first direction. The first pillar includes a first lower end portion and a first extension portion. The first lower end portion is disposed inside the first insulating film. The first extension portion is disposed inside the stacked body.

A vertical FET, including a source layer, a channel layer, a drain layer and a gate dielectric, the source layer being coupled with a source electrode, the channel layer being deposited on top of the source layer, the drain layer being deposited on top of the channel layer and being coupled with a drain electrode, the gate dielectric being conformally deposited within a cylindrical niche through the drain layer down to the channel layer, the gate dielectric being encircled by the drain layer, the gate dielectric being coupled with a gate electrode deposited within the cylindrical niche, when a threshold voltage Is applied to the gate electrode a channel is formed between the source layer and the drain layer, a length of the channel corresponding to a thickness of the channel layer and a width of the channel corresponding to a perimeter of the cylindrical niche.

According to example embodiments, an electronic device includes channel layer including a graphene layer electrically contacting a quantum dot layer including a plurality of quantum dots, a first electrode and a second electrode electrically connected to the channel layer, respectively, and a gate electrode configured to control an electric current between the first electrode and the second electrode via the channel layer. A gate insulating layer may be between the gate electrode and the channel layer.

An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel. An integrated circuit including the circuit is described.

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.

A Tunnel Field-Effect Transistor (TFET) is provided comprising a source-channel-drain structure of a semiconducting material. The source-channel-drain structure comprises a source region being n-type or p-type doped, a drain region oppositely doped than the source region and an intrinsic or lowly doped channel region situated between the source region and the drain region. The TFET further comprises a reference gate structure covering the channel region and a source-side gate structure aside of the reference gate structure wherein the work function and/or electrostatic potential of the source-side gate structure and the reference work function and/or electrostatic potential of the reference gate structure are selected for allowing the tunneling mechanism of the TFET device in operation to occur at the interface or interface region between the source-side gate structure and the reference gate structure in the channel region.

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.

A field effect transistor includes a semiconductor stack including a channel provided on a border between a first nitride semiconductor and a second nitride semiconductor provided on the first nitride semiconductor in a stacking direction. A source electrode, a gate electrode, and a drain electrode are disposed on the semiconductor stack. The gate electrode is disposed between the source electrode and the drain electrode. At least one hole is provided to pass through the channel from the first nitride semiconductor to the second nitride semiconductor to provide channel paths from the gate electrode to the drain electrode. A minimum distance of the channel paths is longer than a minimum distance between the gate electrode and drain electrode viewed in the stacking direction. The insulating member is filled in the at least one hole and has a breakdown field strength higher than a breakdown field strength of the semiconductor stack.

A semiconductor device includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, a source electrode in contact with the second oxide semiconductor film, a drain electrode in contact with the second oxide semiconductor film, a metal oxide film over the second oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the metal oxide film, and a gate electrode over the gate insulating film. The metal oxide film contains M (M represents Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) and Zn. The metal oxide film includes a portion where x/(x+y) is greater than 0.67 and less than or equal to 0.99 when a target has an atomic ratio of M:Zn=x:y.

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.